Pre-Metal Dielectric MIM Capacitor Layout Without Deep Trenching
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Solution Overview
Problem
Current methods for increasing the surface capacity of capacitive elements in integrated circuits, such as deep trench etching, are limited by etching time and equipment availability, making it costly and restrictive to enhance capacitive value.
Innovation Solution
Incorporating metal-insulator-metal (MIM) capacitive structures within the pre-metal dielectric region of integrated circuits, utilizing a conductive layer of polycrystalline silicon with a metal silicide diffusion barrier, and forming trenches to increase the interface area between metal layers, allowing for co-integration with MOS-type capacitive structures without additional substrate space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep trench etching is used to increase surface capacity, then capacitive value increases, but etching time increases proportionally with depth
Solution Approach 1:
The patent transitions from increasing capacitive value through vertical depth (single dimension) to utilizing horizontal planar integration within the pre-metal dielectric region (two-dimensional expansion). By forming MIM capacitive structures in the lateral space of the pre-metal dielectric layer rather than etching deeper vertically, the solution achieves higher surface capacity without proportionally increasing etching time.
2Quantity of substance
If deep trench etching is used to increase surface capacity, then capacitive value increases, but equipment cost and availability requirements increase
Solution Approach 1:
The patent makes the pre-metal dielectric region serve multiple functions: it continues to provide electrical insulation between the conductive layer and first metal level, and simultaneously hosts MIM capacitive structures to increase surface capacity. This multi-functional use of existing pre-metal dielectric region eliminates the need for specialized deep trench etching equipment while achieving enhanced capacitive value.
3Quantity of substance
If MIM capacitive structures are formed in the pre-metal dielectric region, then additional capacitive interface is obtained without additional substrate space, but spatial constraints from other elements must be managed
Solution Approach 1:
The patent embeds MIM capacitive structures within the volume of the pre-metal dielectric region, nesting them among other circuit elements. The capacitive structures are formed in the lateral space of the pre-metal dielectric layer, effectively utilizing the existing three-dimensional space without requiring additional substrate area, similar to nesting one object within another's volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances capacitive value while maintaining compatibility with existing production chains, reducing costs and spatial constraints, and enabling the formation of both MIM and MOS capacitive structures within the same integrated circuit, effectively increasing overall capacitive performance without occupying additional substrate space.
Implementation Method 1
the first metal layer comprises a diffusion barrier layer in chemical bond with the thin layer of metal silicide
Data Source
AI summary
An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.