Premolded Leadframe Semiconductor Package with Flush Contacts
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Solution Overview
Problem
Conventional semiconductor devices, such as DC-DC converters, face challenges with increased size and board area requirements, necessitating the need for more compact solutions that reduce space and cost.
Innovation Solution
A semiconductor device comprising a premolded leadframe with flush electrical contacts and a semiconductor package laterally displaced on the leadframe, allowing for a compact System-in-Package (SiP) configuration, including a semiconductor chip and electrical contacts, which reduces the overall device size and board area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional DC-DC converters use integrated half bridges and passive electronic components arranged side by side on a printed circuit board, then the device can be assembled, but the device size and board area requirement increase
Solution Approach 1:
The patent merges the half bridge circuit and passive electronic components into a single integrated semiconductor package, eliminating the need for separate PCB mounting of multiple components. This consolidation directly reduces the board area while maintaining assembly capability through the unified package structure.
Solution Approach 2:
The patent embeds the semiconductor package containing the half bridge circuit within a leadframe structure, creating a nested configuration where one component is housed within another. This nesting approach minimizes the overall footprint and reduces the space required on the printed circuit board.
2Area of stationary object
If leadframe based QFN packages are used, then the device footprint is reduced, but the electrical contact arrangement becomes complex
Solution Approach 1:
The patent segments the electrical contacts into distinct groups: leadframe contacts extending from the main surface and semiconductor package contacts on the opposite surface. This segmentation allows for simplified, independent routing of electrical connections while maintaining a compact footprint.
Solution Approach 2:
The patent utilizes three-dimensional spatial arrangement by placing the semiconductor package on the opposite main surface of the leadframe, with electrical contacts extending in different directions. This dimensional approach simplifies the electrical contact arrangement compared to planar QFN designs by distributing contacts across multiple surfaces and orientations.
3Volume of stationary object
If the semiconductor package is arranged on the main surface and laterally displaced to the electrical contact, then the device size is reduced, but the electrical contact alignment precision requirement increases
Solution Approach 1:
The patent incorporates preliminary alignment features during the manufacturing process, where the leadframe and semiconductor package are designed with pre-defined contact interfaces. This preliminary preparation ensures that electrical contacts align correctly during assembly, reducing the actual alignment precision requirements during final manufacturing.
Solution Approach 2:
The patent introduces an intermediary structure (the leadframe main surface) that mediates between the electrical contacts of the leadframe and the semiconductor package. This intermediary provides a stable reference plane that facilitates precise alignment while allowing lateral displacement, thereby reducing the overall device size without compromising alignment precision.
Data Source
AI summary
A semiconductor device includes a premolded leadframe, including a main surface, at least one electrical contact extending out of the main surface, and an opposite main surface arranged opposite to the main surface. The semiconductor device further includes a semiconductor package arranged on the main surface and laterally displaced to the at least one electrical contact of the premolded leadframe. The semiconductor package includes a semiconductor chip and at least one electrical contact. Surfaces of the at least one electrical contact of the premolded leadframe and the at least one electrical contact of the semiconductor package facing away from the main surface are flush.