Pre-OS Memory Cacheability via MTRR and PAT Configuration
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Solution Overview
Problem
Current information handling systems lack fine-grained memory cacheability during the pre-OS operating environment, leading to inefficiencies and increased latency in processing and boot times, particularly for memory regions used by I/O devices and graphical user interface interactions.
Innovation Solution
The system employs a Memory Type Range Register (MTRR) and Page Attribute Table (PAT) to define specific cacheability settings for memory regions, enabling fine-grained memory typing and optimizing cache operations by allowing settings such as write combining and write protected for certain memory types, which are dynamically managed by the pre-OS code before passing execution to the boot loader.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fine-grained memory cacheability is implemented during pre-OS environment, then processing speed and boot time are improved, but device complexity increases due to additional register setup and configuration
Solution Approach 1:
The patent applies preliminary action by configuring memory type ranges and cacheability settings during the pre-OS environment before the operating system boots. The pre-OS code sets up MTRR registers and PAT tables to define memory types (such as write-combining, write-protected, and write-back) for specific memory regions, enabling optimized cache operations to be in place before general system operations begin, thus improving processing speed from the outset
Solution Approach 2:
The patent implements local quality by applying different cacheability settings to different memory regions based on their specific requirements. Instead of uniform cache management, the system configures specific memory types for specific memory ranges (e.g., write-combining for frame buffers, write-protected for I/O regions), allowing each memory region to have optimized cache behavior tailored to its functional needs, thereby improving overall system productivity
2Loss of time
If fine-grained memory cacheability is implemented during pre-OS environment, then boot time is reduced, but device complexity increases due to additional configuration steps
Solution Approach 1:
The patent reduces boot time by performing memory configuration actions during the pre-OS stage. The system sets up MTRR (Memory Type Range Register) and PAT (Page Attribute Table) configurations before the OS bootloader executes, ensuring that cache operations are optimized from the very beginning of system operation. This preliminary configuration eliminates the need for time-consuming memory setup during OS initialization, directly reducing overall boot time
Solution Approach 2:
The patent changes memory parameters dynamically during the pre-OS environment by configuring MTRR registers and PAT entries to define different memory types for different address ranges. The pre-OS code modifies memory attributes (such as cacheability, write-combining, write-protect) for specific memory regions, enabling optimized cache behavior that accelerates boot operations and early system performance without requiring complex hardware modifications
Data Source
AI summary
An information handling system includes a memory with a cache, and a processor to execute pre-operating system (pre-OS) code before the processor executes boot loader code. The pre-OS code sets up a Memory Type Range Register (MTRR) to define a first memory type for a memory region of the memory, sets up a page attribute table (PAT) with an entry to define a second memory type for the memory region, disables the PAT, and pass execution by the processor to the boot loader code. The first memory type specifies a first cacheability setting on the processor for data from the memory region, and the second memory type specifies a second cacheability setting on the processor for data from the memory region.