Pre-patterned Substrate for Printed Electronics with Interdigitated Lines
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Solution Overview
Problem
Conventional ink jetting technologies for fabricating electronic devices on flexible substrates result in large transistor channel lengths and wide conductive lines, leading to high W/L ratios, increased circuit size, and significant overlap parasitic capacitance, which hinder device performance and speed.
Innovation Solution
A pre-patterned substrate with interdigitated line structures at the micrometer or nanometer scale allows for precise placement of semiconductor inks, reducing channel length and width, thereby achieving a higher W/L ratio and minimizing overlap capacitance, enabling smaller, faster, and more efficient electronic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional ink jetting technology is used to fabricate transistors, then the manufacturing process is simple and low cost, but the channel length and line width are large resulting in high W/L ratio and large circuit size
Solution Approach 1:
The substrate is pre-patterned with interdigitated conductive lines and insulating regions before the printing process. This preliminary structuring enables precise definition of channel length and line width without requiring high-precision printing, thereby resolving the contradiction between manufacturing simplicity and dimensional precision.
Solution Approach 2:
The substrate is divided into repetitive pattern segments with interdigitated lines and insulating regions. This segmentation allows each printed transistor to inherit precise geometric definitions from the substrate pattern, enabling small channel lengths and line widths while maintaining simple printing processes.
2Power
If large W/L ratio is used to achieve desired device performance with organic semiconductors, then the current handling capacity is sufficient, but the circuit size becomes larger than desirable
Solution Approach 1:
The substrate pre-defines short channel lengths through its interdigitated line pattern. This preliminary action allows achieving high W/L ratios and sufficient current handling capacity while maintaining small circuit sizes, as the precise channel dimensions are inherited from the substrate structure rather than the printing process.
3Ease of manufacture
If wide conductive lines are used in conventional jetting technique, then the manufacturing is easier, but the overlap area between source/drain and gate increases resulting in large parasitic capacitance
Solution Approach 1:
The substrate is pre-patterned with narrow interdigitated conductive lines before printing. This preliminary action defines small overlap areas between source/drain and gate regions, thereby minimizing parasitic capacitance while maintaining ease of manufacture through simple printing processes that deposit semiconductor material over the pre-defined patterns.
Solution Approach 2:
The conductive lines are segmented into interdigitated patterns with insulating regions between them. This segmentation reduces the overlap area between adjacent conductive elements, minimizing parasitic capacitance while keeping the manufacturing process simple.
Data Source
AI summary
A pre-patterned substrate has a supporting material, a plurality of segments on the supporting material, a plurality of interdigitated line structures within each segment to allow formation of features, and an isolation region between the segments.