Prepended Parity Encoder for Early Serial Error Detection
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Solution Overview
Problem
In digital data serial communication systems, appended parity data cannot detect errors early in transmission, as it is received only after all data sets have been received, making it impossible to detect communication errors promptly.
Innovation Solution
A logic circuit that generates and prepends parity data to the data stream, allowing for error detection during initial communication by shifting and calculating parity bits in parallel with the data, using a shift circuit, parity generator, and output selection circuit to transmit prepended parity data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity data is appended to the end of data transmission, then the transmitter can dynamically calculate parity while transmitting, but the receiver cannot detect errors until all data is received
Solution Approach 1:
The patent inverts the conventional parity data positioning by transmitting parity data before the actual data instead of appending it after. The encoder calculates parity for N sets of data and transmits the parity data first, followed by the N sets of data. This inversion allows the receiver to have parity data available immediately for early error detection during the initial reception period, resolving the contradiction between maintaining dynamic calculation capability and enabling timely error detection.
Solution Approach 2:
The patent applies preliminary action by pre-calculating and pre-transmitting parity data before the main data transmission. The encoder dynamically calculates parity data for N sets of data and transmits it in advance. This preliminary transmission of parity information enables the receiver to perform error detection during the initial period of data reception, rather than waiting until all data is received, thus reducing error detection delay while maintaining reliability.
2Reliability
If parity data is prepended to data transmission, then early error detection is enabled, but the circuit complexity increases
Solution Approach 1:
The patent segments the data transmission into distinct units of N sets of data, where parity is calculated for each segment. The encoder processes data in blocks of N sets, calculates parity for each block, and transmits them sequentially. This segmentation allows the use of simpler circuitry that processes data in manageable units rather than requiring complex continuous processing, reducing overall circuit complexity while enabling early error detection for each segment.
Solution Approach 2:
The patent implements a simplified parity calculation that focuses on the essential function of error detection without over-engineering the circuit. By using a straightforward parity generation approach that processes N sets of data and generates corresponding parity data, the circuit achieves the necessary reliability improvement without excessive complexity. The solution provides just enough computational capability for early error detection without adding unnecessary circuit elements.
Data Source
AI summary
A prepended parity data encoder is loaded with sets of data and constant data, which are used for parity calculation. A shift circuit shifts each of the plural sets of data and the constant data, one bit at a time in parallel. When the constant data is output from the shift circuit, a parity generator dynamically generates prepended parity data based on the constant data and the plural sets of data.