Prescaler Clock Generation With Aligned Edges Across Frequencies
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Solution Overview
Problem
Conventional synchronous digital circuits face challenges in generating multiple clocks with differing frequencies that are not synchronous relative to each other, requiring synchronizers and complicating layout considerations.
Innovation Solution
A system utilizing multiple prescalers to generate clock signals with predetermined frequencies, where each prescaler is run-time configurable and uses ripple counters to ensure that the rising edges of the clock signals are aligned, eliminating the need for synchronizers and allowing modular design without disrupting existing clock properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clocks are generated from a reference clock with differing frequencies, then frequency diversity is achieved, but synchronicity between clocks deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the generation of multiple clock signals from the reference clock before they are distributed to different circuit blocks. The synchronizer circuit aligns the phases of all generated clock signals at their source, ensuring that despite frequency differences, all clocks maintain synchronized rising edges throughout operation. This preliminary synchronization eliminates the need for additional synchronizers at each clock consumer.
2Reliability
If synchronizers are added to synchronize multiple clocks, then synchronicity is improved, but device complexity increases
Solution Approach 1:
The patent merges the synchronization function into the clock generation stage itself, combining multiple clock generation and synchronization operations into a single integrated circuit block. Instead of distributing unsynchronized clocks and adding synchronizers at multiple downstream locations, all synchronization is performed once at the source where clocks are generated, reducing overall circuit complexity.
Solution Approach 2:
The synchronizer circuit performs a universal synchronization function for all multiple clock signals generated from the reference clock. This single multi-functional synchronizer replaces what would otherwise require multiple individual synchronizer circuits at different locations in the digital circuit, reducing device complexity while maintaining synchronicity across all clock domains.
3Productivity
If conventional clock generation methods are used, then frequency generation is achieved, but layout complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the generation of multiple clock signals from the reference clock before they are distributed to different circuit blocks. The synchronizer circuit aligns the phases of all generated clock signals at their source, ensuring that despite frequency differences, all clocks maintain synchronized rising edges throughout operation. This preliminary synchronization eliminates the need for additional synchronizers at each clock consumer.
Data Source
AI summary
A method and system for generating multiple clock signals from a reference clock signal are provided. In one implementation, the system includes a reference clock to generate a reference clock signal having a first frequency, a first prescaler to receive the reference clock signal and generate a first output clock signal having a pre-determined frequency relative to the first frequency of the reference clock signal, and a second prescaler to receive the first output clock signal and generate a second output clock signal having a second pre-determined frequency relative to the first pre-determined frequency of the first output clock signal. The first output clock signal is substantially synchronous to the second output clock signal.