Prescaler Clock Division Without Duty-Cycle Dependency
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Solution Overview
Problem
Conventional prescaler circuits in digital frequency synthesizers rely on the duty cycle of the input clock signal, limiting their maximum operating speed and causing issues like stuck states and high-frequency glitches, especially in digital mobile communication devices.
Innovation Solution
The proposed circuitry clocks flip-flops on a single edge of the input clock signal, using feedback mechanisms to independently control frequency division without relying on duty cycle, eliminating half-cycle operations and requiring no dedicated startup circuitry, thus preventing blocking and glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional prescaler circuits use half-cycle operation dependent on duty cycle, then frequency division can be achieved, but maximum operating speed is limited and stuck states occur
Solution Approach 1:
The circuit is divided into two separate full-cycle paths: one path handles the divide-by-2 operation using flip-flop 202 clocked on rising edges, while another path handles the divide-by-3 operation using flip-flop 204 clocked on falling edges. This segmentation eliminates the half-cycle operation dependency and allows independent reliable operation of each division path.
Solution Approach 2:
Instead of using a single edge-triggered flip-flop that creates half-cycle operation, the invention uses two edge-triggered flip-flops triggered on opposite edges of the clock signal. This inversion of the triggering approach ensures full-cycle operation for both paths, eliminating stuck states and enabling higher operating speeds.
2Adaptability or versatility
If dual modulus prescaler uses clock pulse swallowing technique, then frequency division ratio can be changed, but operation becomes dependent on duty cycle of input clock signal
Solution Approach 1:
The detector circuit acts as an intermediary that monitors the outputs of both divide-by-2 and divide-by-3 paths. Based on the detector's output, the circuit selectively activates either the divide-by-2 path or the divide-by-3 path, enabling flexible frequency division ratios without duty cycle dependency. The intermediary detector ensures proper selection based on the desired division ratio.
3Productivity
If prescaler circuit blocks clock signal edges, then frequency division is achieved, but high-frequency glitches occur
Solution Approach 1:
Both divide-by-2 and divide-by-3 paths operate continuously on full clock cycles without blocking any edges. The rising edge path and falling edge path both maintain continuous operation, eliminating the intermittent blocking that causes high-frequency glitches. This continuous operation ensures smooth frequency division without harmful artifacts.
Data Source
AI summary
Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop.