Multi-Modulus Prescaler Divider for Fractional-N Linearity
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Solution Overview
Problem
Conventional fractional-N frequency synthesizers experience nonlinearity due to modulated delay in frequency dividers, leading to degraded noise performance caused by different switching patterns and power supply disturbances.
Innovation Solution
A frequency divider employing a multi-modulus prescaler and programmable counter, which generates a single non-divide-by-N pulse early in the division period, maximizing the time for divide-by-N pattern and minimizing transients, thereby improving modulation linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dual modulus prescaler is used in a fractional-N frequency synthesizer, then the frequency division function is achieved, but modulation linearity is degraded due to divisor-specific transients and modulated delay
Solution Approach 1:
The frequency division operation is segmented into two distinct phases: a first portion where division by N is performed, and a second portion where division by N+1 is performed. This segmentation allows the circuit to handle different division ratios in separate time intervals, reducing the impact of divisor-specific transients on overall modulation linearity while maintaining the required frequency synthesis functionality
Solution Approach 2:
The circuit prepares and switches between different prescaler configurations (divide by N and divide by N+1) in advance according to the fractional division ratio requirements. By pre-configuring the prescaler modes and switching between them systematically, the circuit minimizes transient effects and modulated delay that would otherwise degrade modulation linearity and noise performance
2Adaptability or versatility
If different switching patterns are used in the frequency divider, then frequency division flexibility is improved, but nonlinearity increases due to power supply disturbances
Solution Approach 1:
The frequency divider employs periodic switching between divide-by-N and divide-by-(N+1) operations based on the sigma-delta modulator output. This periodic action systematicaly distributes the switching events over time, allowing power supply disturbances to be averaged out rather than accumulating, thereby maintaining modulation linearity while achieving the required frequency division flexibility for fractional-N synthesis
Data Source
AI summary
A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N−1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.