Presettable Counting Circuit for Synchronized High-Speed Address Counting
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Solution Overview
Problem
Conventional high-speed counters are limited in their ability to input random data and control clock signals, leading to operational errors due to fixed reset states and potential skew issues when constructing larger counting circuits.
Innovation Solution
A counting circuit design incorporating additional flip-flops and logic gates that allow for arbitrary initial value setting and synchronized clock signal control, enabling flexible operation and error prevention in high-speed counting applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional high-speed counters with fixed reset states are used, then the counter structure is simple, but the ability to input random data is limited and operational errors occur
Solution Approach 1:
The patent applies preliminary action by pre-setting the initial state of flip-flops through preset terminals before counting operations begin. This allows the counter to start from any desired value rather than always from zero, enabling random data input capability while maintaining the simplicity of the ring counter structure.
Solution Approach 2:
The patent introduces dynamic control signals (preset control signals) that can dynamically change the initial state of the counter based on external inputs. This makes the counter adaptable to different starting values and random data inputs while preserving the core simple ring counter architecture.
2Quantity of substance
If multiple high-speed counters are coupled to construct larger counting circuits, then the counting capability is enhanced, but clock synchronization issues and operational errors arise due to skew
Solution Approach 1:
The patent segments the large counting circuit into multiple independent high-speed counter units, each with its own preset control mechanism. This segmentation allows each unit to be independently synchronized and controlled, reducing the impact of skew between units while maintaining overall enhanced counting capability.
Solution Approach 2:
The patent implements feedback mechanisms where the output of one counter unit can influence the preset control of subsequent units. This feedback ensures proper synchronization and timing relationships between coupled counters, preventing operational errors due to skew while maintaining reliable clock synchronization across the entire system.
3Ease of operation
If the counter always starts from a fixed reset state, then the circuit control is simple, but flexibility in counting operations is reduced
Solution Approach 1:
The patent makes the counter circuit universal by adding preset terminals that can accept various initial values. The same basic ring counter structure can now perform multiple functions: counting from zero, counting from random values, and adapting to different starting conditions, all while maintaining simple circuit control through unified preset control signals.
Data Source
AI summary
A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal and outputs a signal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.