Pre-tweak Value Cache for Low-Latency Memory Encryption
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Solution Overview
Problem
Processor-external memory systems in automotive applications face latency issues due to long access times and security vulnerabilities, with existing encryption algorithms like AES-XTS unable to efficiently encrypt or decrypt arbitrary memory blocks within a memory sector, leading to variable decryption latency and excessive data processing.
Innovation Solution
A data cryptographic device is implemented with a pre-tweak generator, cache memory, and a block cipher (AES-XTS circuit) that allows for low-latency encryption and decryption of arbitrary memory blocks by using a pre-tweak value cache and tweak generator to optimize memory access and provide secure encryption and authentication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing encryption algorithms like AES-XTS are used to encrypt memory blocks, then security is improved, but decryption latency increases and becomes variable
Solution Approach 1:
The patent pre-calculates and stores tweak values for all possible memory block addresses within a sector in a lookup table during system initialization. When decryption is needed, the appropriate tweak value is immediately retrieved from the table without requiring real-time calculation, thus eliminating variable latency while maintaining AES-XTS security.
2Reliability
If encryption is performed on arbitrary memory blocks within a sector, then data security is improved, but processing time increases excessively
Solution Approach 1:
The patent pre-computes all necessary tweak values for every possible memory block address in a sector during system initialization and stores them in a lookup table. This allows arbitrary memory blocks to be encrypted or decrypted immediately by simply looking up the pre-computed tweak value, avoiding excessive processing time while maintaining security for any memory block.
3Reliability
If real-time tweak value calculation is performed for each memory access, then encryption security is maintained, but access latency increases
Solution Approach 1:
The patent calculates and stores all possible tweak values in a lookup table during system initialization. During memory access operations, the appropriate tweak value is immediately retrieved from the table based on the memory block address, eliminating real-time calculation overhead while maintaining the security properties of AES-XTS encryption.
Solution Approach 2:
The patent creates a copy of all possible tweak values in a lookup table during initialization, allowing the original calculation logic to be replaced by simple table lookups during runtime. This copying approach trades initialization time for significantly faster access operations while preserving encryption security.
Data Source
AI summary
A data cryptographic device may include a pre-tweak generator to generate pre-tweak values, a pre-tweak value cache memory to store one or more pre-tweak values generated by the pre-tweak generator, and a pre-tweak value selector to check whether a pre-tweak value for an input memory address is stored in the pre-tweak value cache memory. The data cryptographic device may further include a tweak generator to generate a tweak value based on the selected pre-tweak value, and a block cipher to perform at least one block cipher algorithm to at least one of encrypt data, encrypt and authenticate data, decrypt encrypted data, decrypt and verify encrypted and authenticated data, using a cryptographic key and the generated tweak value.