Pre-Write Lock Control for Concurrent Data Addressing
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Solution Overview
Problem
Existing data read-write control technologies face inefficiencies due to long addressing processes when dealing with large data volumes, leading to reduced concurrency efficiency and conflicts between write operations, which block read operations for extended periods.
Innovation Solution
Implementing a pre-write lock mechanism that allows processes to perform addressing tasks before actual write operations, enabling concurrent read and write operations by using pre-write identification bits to manage lock requests and prioritize addressing tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read-write lock is configured to ensure data accuracy and avoid write conflicts, then data accuracy is improved, but read operations are blocked during the addressing process, reducing concurrency efficiency
Solution Approach 1:
The patent segments the write operation into two distinct phases: an addressing phase (where the address of the editing element is determined) and an actual write phase (where the data is modified). Different lock strategies are applied to each phase - read locks are permitted during the addressing phase to maintain concurrency, while exclusive write locks are enforced during the actual write phase to ensure data accuracy. This segmentation resolves the contradiction by allowing concurrent reads during address determination while protecting the critical write operation.
Solution Approach 2:
The patent implements preliminary action by completing the addressing process (determining the address of the editing element) before acquiring the write lock and performing the actual write operation. During this preliminary addressing phase, multiple read operations can proceed concurrently without being blocked. Only after the address is determined does the system acquire exclusive write access, minimizing the duration of lock holding and maximizing concurrency efficiency while still ensuring data accuracy during the critical write moment.
2Reliability
If read operations are blocked during the addressing process to ensure data accuracy, then data accuracy is improved, but the efficiency of read-write data is greatly reduced
Solution Approach 1:
The patent divides the data access operation into two separable stages: address determination (addressing process) and data modification (write process). During the address determination stage, the system allows concurrent read operations to proceed without blocking, improving read-write efficiency. The exclusive lock is only acquired during the brief data modification stage, ensuring data accuracy only when necessary. This segmentation eliminates the need to block reads during the potentially time-consuming addressing process while maintaining data integrity during the actual write operation.
3Productivity
If multiple processes operate on the same data simultaneously to improve editing efficiency, then editing efficiency is improved, but write operations between different processes may conflict with each other
Solution Approach 1:
The patent applies preliminary action by having processes determine their target addresses and prepare their write operations before acquiring exclusive write locks. During this preparation phase, multiple processes can independently perform addressing and even read operations concurrently, improving editing efficiency. Once a process has determined its target address and is ready to write, it acquires an exclusive write lock at that specific address, ensuring write operation consistency. This approach allows maximum parallelism during the addressing phase while maintaining strict serialization only during the actual write operations.
Data Source
AI summary
The present application is suitable for a technical field of data processing, and provides a data read-write control method and an electronic device. The method includes: determining read-write parameters of target data, in response to a pre-write lock application request for the target data initiated by a first process; if the pre-write identification bit is a first bit value, feedbacking a pre-write approval instruction to the first process, setting the pre-write identification bit to a second bit value, and controlling the first process to perform a pre-write operation based on a requested pre-write lock; and performing a data editing operation on the target data, in response to a write lock application request for the target data initiated by the first process. By the method, mutual conflicts between write operations can be avoided, and exclusive duration of data during addressing can be reduced, thereby improving a shared reading capability of data.