Primary Director Logical Device Low Latency
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Solution Overview
Problem
Current data storage systems face challenges in achieving low latency and high performance for logical devices due to inefficient I/O operation processing and data mirroring across distributed global memory, leading to increased complexity and potential failures in data access.
Innovation Solution
A method and system for processing I/O operations by designating a primary director for each logical device, which locally accesses a cache location within a distributed global memory, and performing mirroring of cached write data across multiple cache locations within the same or different engines, using a cache slot allocation algorithm to optimize data access paths and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is mirrored across multiple cache locations in distributed global memory, then data integrity and reliability are improved, but access latency and system complexity increase
Solution Approach 1:
The patent segments the distributed global memory into multiple cache locations across different directors, with each director maintaining local cache copies. This segmentation allows parallel access to data segments, improving reliability through redundancy while managing latency through localized access paths.
Solution Approach 2:
The system performs preliminary data mirroring to cache locations before actual I/O operations occur. By pre-positioning data in multiple cache locations across directors, the system ensures data is readily available when needed, improving reliability without incurring latency during actual access operations.
2Productivity
If a primary director is designated for each logical device, then I/O operation efficiency is improved, but system complexity and failure points increase
Solution Approach 1:
The primary director is designed to handle multiple functions including I/O operation processing, cache management, and failover coordination. This multi-functionality improves I/O efficiency by consolidating control while managing complexity through a standardized universal director architecture that can be replicated across the system.
Solution Approach 2:
The primary director acts as an intermediary between hosts and the distributed global memory system. It mediates all I/O operations, simplifying the interface for hosts while managing the complexity of distributed memory access internally. The intermediary role allows for optimized access paths without exposing complexity to external systems.
3Speed
If cache locations are distributed across multiple directors, then data access speed is improved, but coordination overhead and system complexity increase
Solution Approach 1:
Each director is given local cache locations with optimized access characteristics for that specific director. This local quality allows directors to access their local cache locations at high speed without coordination overhead, while the system as a whole achieves distributed access capability. The local optimization eliminates the need for complex inter-director coordination for local accesses.
Solution Approach 2:
The patent introduces a new dimension of organization by distributing cache locations across multiple directors in the director dimension, rather than simply expanding memory capacity in a single director. This dimensional change allows parallel access paths while managing coordination through a structured director hierarchy and standardized inter-director communication protocols.
Data Source
AI summary
A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.