Prime-Level Memory Cells With Finite-Field Error Detection
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Solution Overview
Problem
Increasing the number of storage levels in memory cells to enhance memory density leads to reliability issues due to decreased distance between voltage levels, making memory cells more prone to corruption mechanisms, which existing error detection and correction methods struggle to address effectively.
Innovation Solution
Implementing multi-level memory cells with a non-binary prime number of storage levels, such as 3, 5, 7, or 9, and using finite field arithmetic for error detection and correction, including the BCH algorithm, to enhance error detection and correction capabilities while maintaining comparable ECC overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of storage levels in memory cells is increased to enhance memory density, then storage capacity is improved, but the distance between voltage levels decreases making memory cells more prone to corruption mechanisms
Solution Approach 1:
The patent changes the fundamental parameter of storage level organization from conventional binary-based systems (2, 4, 8 levels) to non-binary prime number-based systems (3, 5, 7, 9 levels). This parameter change optimizes the voltage level distribution to maintain greater effective distance between adjacent levels, thereby improving reliability while preserving high storage capacity. The prime number basis creates more robust voltage margins that are less susceptible to corruption mechanisms.
2Reliability
If multi-level memory cells with non-binary prime number of storage levels are implemented, then error detection and correction capabilities are improved, but device complexity increases
Solution Approach 1:
The patent replaces complex hardware-based error detection and correction mechanisms with software-based finite field arithmetic operations. By implementing ECC algorithms in the logical/software domain rather than requiring complex hardware circuits, the system achieves enhanced error detection and correction capabilities while minimizing the increase in physical device complexity. The finite field mathematics provides robust error handling through computational algorithms rather than additional hardware layers.
3Reliability
If conventional error detection and correction methods are used on multi-level memory cells, then some errors can be detected, but the methods struggle to address errors effectively due to decreased voltage level distance
Solution Approach 1:
The patent applies preliminary error detection and correction coding before data is written to the multi-level memory cells. By pre-encoding the data with ECC codes based on finite field arithmetic, the system prepares correction capability in advance. This preliminary action allows the system to combat voltage-level-induced corruption effectively, as the encoded redundancy is specifically designed to detect and correct the types of errors that arise from decreased voltage level distances in high-density multi-level cells.
Data Source
AI summary
Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed.