Prime-Number Memory Bank Architecture for DSP Contention
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Solution Overview
Problem
Digital signal processing systems face challenges in providing fast memory access for diverse real-time data standards due to the limitations of dedicated memory devices, which restrict their flexibility and configurability.
Innovation Solution
A digital signal processing system utilizing a multi-port memory constructed from a prime number of single-port memory devices, allowing concurrent access through a shared memory interface with prioritization and address conversion techniques to minimize contention and optimize memory access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated memory devices are used for each processing element, then memory access speed is improved, but system flexibility and configurability deteriorate
Solution Approach 1:
The patent implements a universal memory interface that can serve multiple processing elements (DSPs, general-purpose processors, hardware peripherals) through a single shared infrastructure. The memory interface is designed to handle different data types and access patterns universally, eliminating the need for dedicated memory devices for each processing element while maintaining fast access through efficient arbitration and buffering mechanisms.
2Adaptability or versatility
If a single shared memory is used for all processing elements, then system flexibility is improved, but memory access speed deteriorates due to contention
Solution Approach 1:
The patent segments the shared memory into multiple banks that can be accessed simultaneously by different processing elements. The memory interface includes separate access ports that can operate in parallel, reducing contention by distributing memory access across multiple independent memory banks. This segmentation allows multiple processing elements to access different memory banks at the same time, maintaining high speed while preserving flexibility.
Solution Approach 2:
The patent introduces a memory interface as an intermediary between processing elements and the shared memory banks. This interface includes arbitration logic that manages access requests, buffers data temporarily, and coordinates simultaneous access to minimize contention. The intermediary layer abstracts the complexity of shared access from the processing elements while optimizing memory access patterns to maintain high speed.
3Speed
If memory devices are tailored for specific data types, then memory access speed is improved, but device complexity and system configurability worsen
Solution Approach 1:
The patent employs configurable memory interface parameters such as access port width, buffer size, and arbitration priority that can be adjusted based on the type of data being processed. Rather than designing different memory devices for different data types, the system changes operational parameters of the universal memory interface to optimize performance for various data structures and access patterns, reducing device complexity while maintaining high speed access.
Data Source
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AI summary
Memory access in a digital signal processing system is described. In one example, the digital signal processing system comprises a multi-port memory that is constructed from a memory interface connected to a number of single-port memory devices. The memory interface provides access ports that processors can use to access data stored on the single-port memory devices using a single address space. A processor can be connected to several access ports, and use these to request access to data at several different memory addresses at the same time. The digital signal processing system is configured such that the total number of single-port memory devices connected to the memory interface is a prime number greater than or equal to three. Because a prime number of memory devices are used, the likelihood of the data for the different memory addresses being on the same single-port memory device is minimised, increasing memory access speed.