Priming Hierarchical Depth Logic in Graphics Processors

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Solution Overview

Problem

Existing graphics processing technologies face inefficiencies in dynamic visibility determination due to the need for re-generation of hierarchical depth data during each frame rendering, which can lead to increased computational load and power consumption.

Innovation Solution

Implementing a heterogeneous processing system that combines CPU or vector processor-based software occlusion culling with hardware hierarchical depth units, where the graphics processor is primed with pre-determined hierarchical depth data generated during a software occlusion culling pass, allowing for reduced re-generation of depth data and earlier culling of geometry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If hierarchical depth data is re-generated during each frame rendering, then visibility determination accuracy is maintained, but computational load and power consumption increase

Engineering Contradiction:
Improvevisibility determination accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by performing occlusion culling computations before the main rendering pipeline. The CPU or vector processor pre-computes hierarchical depth data and determines occluded regions in advance, allowing the GPU to skip rendering entirely in those regions. This upfront computation eliminates the need to re-generate depth data during each frame's rendering phase, reducing real-time computational load and power consumption while maintaining visibility determination accuracy.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If hierarchical depth data is re-generated during each frame rendering, then visibility determination is performed, but computational overhead increases

Engineering Contradiction:
Improvevisibility determinationVSAvoidcomputational overhead
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The system performs occlusion culling computations in advance during a preprocessing phase executed by the CPU or vector processor. Hierarchical depth data is generated beforehand, and occluded regions are identified before the GPU rendering begins. This preliminary computation simplifies the main rendering pipeline by eliminating the need for complex depth data regeneration during frame rendering, thereby reducing computational overhead while maintaining visibility determination capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary preprocessing layer between the scene description and the main rendering pipeline. The CPU or vector processor acts as an intermediary that pre-computes hierarchical depth information and passes it to the GPU. This intermediary step separates the computationally intensive depth analysis from the real-time rendering process, reducing the computational burden on the GPU during frame rendering while preserving accurate visibility determination.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If hardware hierarchical depth units are used, then depth testing performance is increased, but the need for pre-computation is reduced

Engineering Contradiction:
Improvedepth testing performanceVSAvoidtime for depth data generation
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-computing hierarchical depth data using the CPU or vector processor before passing it to the GPU's hardware hierarchical depth unit. This upfront computation allows the hardware depth unit to operate with pre-prepared data, maximizing its performance potential without being bottlenecked by real-time depth data generation. The preprocessing phase eliminates the time penalty that would otherwise accompany hardware-based depth testing, as the computationally intensive portions are already completed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10733695B2Priming hierarchical depth logic within a graphics processor
Publication Date: 2020.08.04 INTEL CORP
  • US10733695B2 patent drawing
  • US10733695B2 patent drawing
  • US10733695B2 patent drawing

AI summary

Embodiments described herein enable a hierarchical-Z unit of a graphics processor to be primed using Hi-Z data generated by occlusion culling operations performed on a general purpose processor. One embodiment provides for instructions to cause operations including performing occlusion culling for a scene via the general purpose processor and storing generated hierarchical-Z data. The Hierarchical-Z data generated during the occlusion culling operations can be shared with the graphics processor and used to prime a hierarchical-Z unit of the graphics processor. The at least a portion of the scene can then be rendered using the hierarchical-Z data after priming the hierarchical-Z unit, improving the effectiveness of hierarchical-Z operations of the graphics processor for the scene.