Primitive Block Rasterization for Tile-Based SIMD Efficiency

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Solution Overview

Problem

Existing tile-based rendering (TBR) graphics processing systems that use untransformed display lists require complex cache systems and inefficient use of SIMD processors due to repeated fetching and transforming of geometry data for multiple tiles.

Innovation Solution

Group untransformed primitives into primitive blocks based on transformed geometry data, fetching and transforming geometry data for entire blocks rather than individual primitives, and caching transformed data for efficient use across multiple tiles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If individual primitives are fetched and transformed separately for each tile, then memory bandwidth requirements are reduced, but cache system complexity increases and SIMD processor efficiency decreases

Engineering Contradiction:
Improvememory bandwidthVSAvoidcache system complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges multiple individual primitive transformations into a single block-level transformation operation. By grouping primitives into blocks and transforming the entire block at once rather than processing each primitive separately, the system reduces the number of memory accesses and transformation operations, thereby simplifying the cache system while maintaining memory bandwidth efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary grouping of primitives into blocks during the geometry processing phase, before the rasterization phase begins. This preliminary organization of data into blocks enables efficient batch processing during rasterization, reducing the need for complex runtime cache management and optimizing SIMD processor utilization.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If individual primitives are transformed separately for each tile, then memory access requirements are minimized, but processor utilization efficiency decreases

Engineering Contradiction:
Improvememory accessVSAvoidprocessor utilization efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent combines multiple separate primitive transformation operations into a single block-level transformation. By processing entire blocks of primitives together using SIMD instructions, the system maximizes processor utilization efficiency while still minimizing memory accesses through the untransformed display list approach that avoids redundant data retrieval.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent ensures continuous productive work by transforming entire blocks of primitives in batches rather than processing individuals separately. This batch processing approach keeps SIMD processors continuously occupied with meaningful work, eliminating idle cycles that would occur during separate primitive transformations, thereby maximizing processor utilization efficiency.

Inventive Principle:
Principle #20Continuity of useful action

3Speed

If transformed geometry data is stored for each tile, then rendering speed improves, but memory requirements increase

Engineering Contradiction:
Improverendering speedVSAvoidmemory requirements
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential information needed for rendering by storing untransformed display lists that reference primitive blocks rather than storing complete transformed geometry data for each tile. This extraction approach allows the system to retrieve only the necessary transformed data during rasterization, reducing memory requirements while maintaining fast rendering speeds through efficient data access patterns.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP3671650B1Primitive block-based rasterization in graphics processing systems
Publication Date: 2026.02.18 IMAGINATION TECH LTD
  • EP3671650B1 patent drawingFigure 1
  • EP3671650B1 patent drawingFigure 2
  • EP3671650B1 patent drawingFigure 3

AI summary

A graphics processing system having a rendering space divided into a plurality of tiles. The system comprises geometry processing logic and rasterization logic. The geometry processing logic is configured to generate transformed position data for each of a plurality of untransformed primitives based on untransformed geometry data associated therewith; group the plurality of untransformed primitives into a plurality of primitive blocks; and generate an untransformed display list for each tile based on the transformed position data. Each untransformed display list comprises: (i) information identifying each untransformed primitive block that comprises at least one untransformed primitive that, when transformed, falls at least partially with the tile; and (ii) for each identified untransformed primitive bock, information identifying the untransformed primitives or transformed primitives related to that untransformed primitive block relevant for rendering the tile. The rasterization logic is configured to fetch, for each primitive block identified in an untransformed display list for a tile, untransformed geometry data for all of the untransformed primitives in that untransformed primitive block; transform the fetched untransformed geometry data to generate transformed geometry data; and render the primitives from the transformed geometry data.