Primitive-Polynomial LFSR Counter for Fast Low-Area Counting
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Solution Overview
Problem
Traditional binary counters face issues with propagation delays and inefficient area consumption due to carry ripple effects and large combinational logic, making them less suitable for high-speed and compact hardware designs.
Innovation Solution
Implementing a multi-bit Linear-Feedback Shift Register (LFSR) counter with exclusive-or logic between flip-flops based on a primitive polynomial, coupled with a shared look-up table and random-access memory to generate unique bit sequences efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional binary counters with Full Adders are used, then counting functionality is achieved, but propagation delay increases due to carry ripple effect
Solution Approach 1:
The patent replaces the mechanical carry-ripple addition mechanism with an LFSR-based sequential shifting mechanism. Instead of using Full Adders that propagate carries sequentially through combinational logic, the invention uses flip-flops that shift bits sequentially on clock edges, eliminating the carry propagation delay inherent in traditional binary counters.
Solution Approach 2:
The invention introduces dynamic clocking where each flip-flop in the LFSR is triggered by the same clock signal, enabling synchronized state transitions. This dynamic approach allows all bits to update simultaneously based on the clock edge, rather than waiting for carry propagation through multiple Full Adder stages, thus improving counting speed.
2Productivity
If traditional binary counters with Full Adders are used, then counting functionality is achieved, but chip area consumption increases due to large combinational logic
Solution Approach 1:
The patent substitutes the complex combinational logic of Full Adders with simpler sequential flip-flop elements and XOR gates for feedback generation. The LFSR structure requires only n flip-flops and a small number of XOR gates for the feedback polynomial, whereas a traditional n-bit binary counter requires multiple Full Adders with extensive combinational logic, significantly reducing chip area.
Solution Approach 2:
The invention changes the fundamental operating parameters of the counter by transitioning from parallel combinational logic evaluation to sequential clocked shifting. This parameter change from combinational to sequential operation allows for more compact hardware implementation while maintaining counting functionality.
Data Source
AI summary
A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.