Print Data Analysis Error Handling in Multi-Core Printing Systems

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Solution Overview

Problem

In multi-core CPU-based printing apparatuses, when an error occurs during the analysis processing of print data, the processing is suspended, leading to potential incomplete output of pages, as conventional systems lack effective error handling mechanisms to manage errors across multiple analyzing units.

Innovation Solution

A printing apparatus with a control unit that receives error notifications from analyzing units and cancels analysis processing in other units only after ensuring all pages prior to the error page have been completed, allowing for optimal error handling and preventing incomplete page outputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-core CPU is applied to analysis processing of print data, then throughput is improved, but error handling becomes complex and may lead to incomplete page output

Engineering Contradiction:
ImprovethroughputVSAvoiderror handling
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the analysis processing into multiple independent analyzing units, each responsible for specific pages. When an error occurs in one unit, other units can continue processing independently, maintaining throughput while enabling selective cancellation of only affected pages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The control unit receives error notifications from analyzing units and uses this feedback to determine whether to cancel processing in other units. This feedback mechanism ensures reliable error handling while maintaining the productivity benefits of multi-core processing.

Inventive Principle:
Principle #23Feedback

2Loss of time

If processing is suspended immediately when error occurs in multi-core system, then error response time is reduced, but pages that would have been output are not output

Engineering Contradiction:
Improveerror response timeVSAvoidpage output completion
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The control unit checks whether pages before the error page have been completed before canceling processing. This preliminary action ensures that completed pages are output while still allowing cancellation of incomplete pages, balancing rapid error response with production completion.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If single-core CPU is used for analysis processing, then error handling is simple, but throughput is limited

Engineering Contradiction:
Improveerror handling complexityVSAvoidthroughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent segments the analysis processing into multiple independent units distributed across cores. Each unit handles specific pages independently, allowing the system to achieve multi-core throughput while maintaining relatively simple error handling through modular architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11055587B2Image forming apparatus having print data analysis, information processing method and storage medium
Publication Date: 2021.07.06 CANON KK
  • US11055587B2 patent drawing
  • US11055587B2 patent drawing
  • US11055587B2 patent drawing

AI summary

An image processing apparatus includes a first analyzing unit configured to analyze at least a first page data of print data, and a second analyzing unit configured to analyze at least a second page data of the print data. In a case where an error occurs in analyzing the second page data by the second analyzing unit before completing analyzing of the first page data, the second analyzing unit stops analyzing the second page data, and the first analyzing unit continues analyzing the first page data until analyzing of the first page data is completed, wherein the first page data proceeds to the second page data in the print data. The first analyzing unit and the second analyzing unit are implemented by one or more processors or circuitry, or a combination thereof.