Print Component Memory Bit Access via Single-Lane Analog Bus
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Solution Overview
Problem
Current printer technologies face challenges in efficiently managing and accessing multiple memory bits for fluid actuators, leading to potential inadvertent signaling and increased complexity, which can affect print quality and security.
Innovation Solution
The use of a single-lane analog bus to connect and measure multiple memory bits in parallel, allowing for simultaneous selection and reading of memory bits across multiple print dies, while implementing an access sequence to prevent inadvertent memory access and sharing circuitry for both fluid actuation and memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If multiple separate bus lanes are used to connect memory bits, then each memory bit can be accessed independently, but the device complexity and number of connections increase
Solution Approach 1:
The patent combines multiple memory bit connections into a single shared bus lane. The print head circuitry multiplexes the connection by selectively activating specific memory bits along the shared lane, allowing multiple memory bits to be accessed through one physical connection rather than requiring separate lanes for each bit.
Solution Approach 2:
The shared bus lane serves multiple functions by being able to connect to and activate any specific memory bit along the lane. The same physical connection is used universally for different memory bits at different times, rather than having dedicated connections for each bit.
2Speed
If memory bits are accessible without restriction, then access speed is fast, but inadvertent signaling and security risks increase
Solution Approach 1:
The system performs preliminary activation of specific memory bits before data transmission occurs. The print head circuitry selectively activates only the intended memory bits along the shared lane prior to signaling, ensuring that even though the lane is shared, only the correct bits are ready to receive or transmit data at any given time.
Solution Approach 2:
Different segments of the shared bus lane have different activation states. The system creates local quality differences by activating specific portions of the lane while keeping others inactive, allowing selective access to particular memory bits while maintaining security against inadvertent signaling to unintended bits.
3Adaptability or versatility
If separate circuitry is used for fluid actuation and memory access, then functional independence is achieved, but device complexity increases
Solution Approach 1:
The print head circuitry is designed with multi-functionality, serving both fluid actuation control and memory bit access through the same shared lane infrastructure. The circuitry can selectively switch between controlling fluid ejection and accessing memory bits, eliminating the need for completely separate circuit paths while maintaining functional independence through selective activation.
Data Source
AI summary
An integrated circuit to drive a number of fluid actuation devices, comprising a circuit configured to have a memory access state which can be set to one of an enabled state and disabled state. The integrated circuit to include a fluid actuation circuit to transmit selection information for a fluid actuation device, the selection information comprising a data state bit. The integrated circuit to include a memory cell array, configured so that each memory cell is accessible by the memory access state being enabled, and the data state bit being set.