Printed Board Control Wire Routing for Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor devices fail to efficiently draw control wires connected to control electrodes of semiconductor chips, leading to floating inductance issues when implementing upper and lower arms for three-phase circuits.
Innovation Solution
A semiconductor device configuration featuring a plurality of semiconductor chips mounted on an insulated circuit board with a printed board, where the printed board includes upper and lower relay pattern layers and common pattern layers, allowing control wires to be efficiently connected between these layers to reduce floating inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control wires are drawn through conventional routing methods in printed boards, then ease of manufacture is maintained, but floating inductance increases leading to poor electrical connection quality
Solution Approach 1:
The patent transitions control wire routing from a planar two-dimensional path on the printed board surface to a three-dimensional path that passes through the insulating layer between upper and lower relay pattern layers. This dimensional change allows control wires to achieve shorter electrical paths and reduced floating inductance while maintaining manufacturability through standard through-hole or via techniques.
Solution Approach 2:
The control wires are nested within the layered structure of the printed board, specifically passing through the insulating layer between the upper and lower relay pattern layers. This nesting approach integrates the control wire routing into the existing board structure, reducing inductance without significantly increasing overall device complexity or manufacturing difficulty.
2Productivity
If traditional 2-in-1 module design is used for three-phase bridge circuits, then device complexity is reduced, but productivity and integration efficiency decrease
Solution Approach 1:
The patent merges six semiconductor chips (three upper arms and three lower arms for three-phase bridge circuits) into a single integrated module, achieving a 6-in-1 configuration. This consolidation integrates all control wire connections and electrical pathways within one module structure, significantly improving productivity and integration efficiency despite the increased internal structural complexity.
Solution Approach 2:
The printed board structure is designed with universal functionality to handle all six semiconductor chips and their control wire connections simultaneously. The upper and lower relay pattern layers with corresponding potential create a universal routing framework that accommodates multiple phases and arms within a single module, enhancing integration efficiency.
Data Source
AI summary
A semiconductor device implements upper and lower arms for three phases by a plurality of semiconductor chips, an insulated circuit board, and a printed board, the printed board includes: a plurality of upper relay pattern layers arranged on one main surface of an insulating layer; an upper common pattern layer arranged on the one main surface of the insulating layer; a plurality of lower relay pattern layers arranged to be opposed to the upper relay pattern layers on another main surface opposite to the one main surface of the insulating layer; and a lower common pattern layer arranged to be opposed to the upper common pattern layer on the other main surface of the insulating layer, and control wires electrically connected to the semiconductor chips are partly provided in regions between the upper relay pattern layers and the upper common pattern layer.