Printed Circuit Board Via Structure for Solderability and Heat Transfer
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Solution Overview
Problem
Poor solderability during the soldering of printed circuit boards due to inadequate heat transfer from the soldering process, leading to thermal stress and potential electrical connection failure.
Innovation Solution
A printed circuit board design with alternating dielectric and conductive layers, incorporating through holes and inner layer vias that enhance heat conduction and prevent short circuits by isolating capacitor terminals, allowing for efficient heat transfer and reducing the risk of electrolyte leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat is generated during soldering, then soldering process can be completed, but heat is not easily transferred to rear surface resulting in poor solderability
Solution Approach 1:
The patent introduces an intermediary heat conduction path through conductive patterns (copper traces) on the circuit board. These conductive patterns act as thermal mediators that facilitate heat transfer from the soldering area to the rear surface of the board, solving the heat transfer problem while maintaining good solderability
Solution Approach 2:
The patent extracts the heat conduction function from the general board structure by specifically designing dedicated heat conduction paths using conductive patterns. This separates the heat transfer function from other board functions, allowing optimized heat management independent of the overall board design
2Reliability
If poor solderability occurs, then thermal stress results in cracks in solder, but electrical connection is eventually lost
Solution Approach 1:
The patent applies beforehand cushioning by designing redundant electrical connection paths through multiple conductive patterns and vias. This creates backup pathways that cushion against the risk of solder joint failure, ensuring electrical connection is maintained even if thermal stress causes cracks in primary solder joints
3Area of stationary object
If capacitor terminals are positioned close together, then space is saved, but short circuit risk increases due to electrolyte leakage
Solution Approach 1:
The patent segments the capacitor terminal arrangement by positioning them in different layers or regions of the circuit board, separated by dielectric materials and conductive patterns. This spatial segmentation prevents electrolyte from causing short circuits between terminals while maintaining compact overall footprint
Solution Approach 2:
The patent utilizes the third dimension (vertical layering) to separate capacitor terminals that would be close in the horizontal plane. By arranging terminals in different layers with appropriate insulation, the design achieves compact 2D footprint while maintaining safe 3D separation to prevent short circuits
4Reliability
If inner layer vias are added to enhance heat conduction, then solderability improves, but device complexity increases
Solution Approach 1:
The patent makes the conductive patterns and vias multi-functional, serving both electrical connection purposes and heat conduction functions. This universality means that adding these features for electrical reasons also provides thermal benefits, avoiding the need for separate dedicated heat conduction structures and thus limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves solderability and reliability by facilitating heat conduction and preventing short circuits, thereby enhancing the durability and performance of the printed circuit board.
Implementation Method 1
heat generated during soldering is not easily transferred to a rear surface
Data Source
AI summary
A printed circuit board includes a plurality of dielectric layers, a plurality of conductive pattern layers, a first through hole, a second through hole, and an inner layer via. The inner layer via penetrates through each dielectric layer from an Mth dielectric layer to the (N-1)th dielectric layer, where M is an integer that is greater than equal to two and less than or equal to (N-1) and has an inner circumferential surface on which an inner layer via conductor is disposed. At least a portion of the inner layer via is disposed in an inner via arrangement region. At least one of the first through hole and the second through hole is connected to the inner layer via with at least one conductive pattern layer that is selected from a second conductive pattern layer to an Nth conductive pattern layer in the plurality of conductive pattern layers.