Printed Interconnects for High-Density 3D IC Packaging
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Solution Overview
Problem
The design and fabrication of electrical interconnects in multi-chip module (MCM) devices with 3D packaging geometries face challenges due to long design cycles, die obsolescence, limited substrate suppliers, and physical constraints such as limited printed wiring board geometries and high input/output demands, which restrict the selection of suitable commercial-off-the-shelf (COTS) components and vertical/horizontal densities.
Innovation Solution
The use of printed interconnects formed from a layer of material to provide electrical connections between substrate and integrated circuit components, with the interconnects printed across a dielectric layer that forms a continuous surface, allowing for efficient integration of COTS components and high-density stacking of ICs, facilitated by additive manufacturing techniques like non-contact jet, inkjet, or extrusion processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional electrical interconnect fabrication methods are used in 3D packaging, then design cycles are extended and component selection is limited, but the patent applies printed interconnects to reduce design cycles and expand component selection flexibility
Solution Approach 1:
The patent replaces traditional mechanical/electrical interconnect fabrication processes with printed interconnect technology. The printed interconnects are formed by depositing conductive material through printing processes, substituting complex mechanical assembly and traditional electrical interconnect fabrication with a more flexible printing-based approach, thereby reducing design cycles and improving ease of manufacture
Solution Approach 2:
The patent changes the fabrication parameters by introducing printed interconnects with variable geometries and configurations. The printed interconnects can be customized in terms of trace width, spacing, and routing patterns, allowing adaptation to different component layouts and reducing design cycle constraints while maintaining manufacturing feasibility
2Quantity of substance
If high I/O and small-pitch COTS IC component integration are demanded, then physical constraints limit component selection and density, but the patent uses printed interconnects to achieve high vertical and horizontal densities
Solution Approach 1:
The patent transitions from traditional planar interconnect layouts to three-dimensional printed interconnect structures. By utilizing vertical stacking and multi-layer printed circuits, the design achieves high component density in both vertical and horizontal directions, overcoming substrate area constraints while integrating high I/O and small-pitch COTS IC components
Solution Approach 2:
The patent segments the interconnect structure into multiple printed layers and modular components. This segmentation allows independent optimization of signal routing, power distribution, and ground planes, enabling high component density integration while maintaining electrical performance and accommodating various substrate geometries
3Ease of manufacture
If printed interconnects are used to enable efficient packing and high density, then fabrication processes must accommodate mechanically sensitive components, but the patent achieves reduced fabrication costs and enhanced design flexibility
Solution Approach 1:
The patent replaces mechanical assembly processes that could damage sensitive components with printed interconnect fabrication. The printing process deposits conductive material in a controlled manner, avoiding mechanical stress and heat exposure that might harm mechanically sensitive components, thereby maintaining reliability while reducing fabrication costs and enhancing design flexibility
Data Source
AI summary
An electrical device with printed interconnects between packaged integrated circuit components and a substrate as well as a method for printing interconnects between packaged integrated circuit components and a substrate are disclosed. An electrical device with printed interconnects may include a dielectric layer forming a continuous surface between a substrate and a terminal face of an integrated circuit component. The electrical device may further include interconnects formed from a layer of material printed across the continuous surface formed by the dielectric layer to connect electrical terminals on the substrate to electrical terminals on the terminal face of the integrated circuit component.


