Printed Nonvolatile Memory Cell Using Segmented Gate Oxides
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Solution Overview
Problem
Existing nonvolatile memory devices based on floating-gate transistors have finite lifetimes due to degradation of charge storage capability during electrical erase processes, limiting their operational cycles to around 10^5 write operations, and require costly and time-consuming masking steps in manufacturing.
Innovation Solution
The development of a nonvolatile memory cell using a printed TFT process flow with a single floating gate and two gate oxides, where semiconductor islands are formed by printing silicon ink and doped dielectric films, eliminating the need for additional dielectric deposition and patterning steps, and allowing for improved carrier mobility and gate oxide interface quality through sequential lateral laser solidification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If electrical erase process is used in floating-gate transistor memory, then memory can be reset or erased, but charge storage capability degrades limiting lifetime to 10^5 write operations
Solution Approach 1:
The gate oxide is segmented into two distinct layers: a first gate oxide layer for charge storage and a second gate oxide layer for tunneling operations. This segmentation allows the charge storage layer to remain undisturbed during erase operations, while the tunneling layer handles the stress of repeated programming/erasing cycles, thereby preserving charge storage capability while maintaining operational functionality.
2Manufacturing precision
If conventional masking steps are used in manufacturing, then precise patterning can be achieved, but manufacturing cost and time increase
Solution Approach 1:
The patent replaces conventional photolithographic masking (a mechanical/optical system) with a direct printing system that deposits patterned materials directly onto the substrate. This printing-based approach eliminates the need for separate masking steps while achieving the required patterning precision, thereby reducing manufacturing complexity, cost, and cycle time.
3Productivity
If printed TFT process flow is used, then manufacturing cost decreases and throughput increases, but process control complexity increases
Solution Approach 1:
The patent combines multiple conventional manufacturing steps into a single printed TFT process flow. The printing system simultaneously performs material deposition, patterning, and doping in one integrated process, eliminating the need for separate masking, deposition, and etching steps. This merging of operations simplifies overall process control while dramatically increasing throughput and reducing manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances retention time and reduces manufacturing costs by eliminating masking steps, achieving reliable electrical characteristics and improved data retention without extra processing steps, enabling higher throughput and lower production costs.
Implementation Method 1
The act of programming the cell to a predetermined state (other than an erased state) involves charging the floating gate with electrons, which causes the turn-on threshold of the memory cell to increase.
Implementation Method 2
The floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer
Implementation Method 3
improved carrier mobility and gate oxide interface quality through sequential lateral laser solidification
Data Source
AI summary
A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.