Printer Chip Terminal Layout for Accurate Short-Circuit Checks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for determining chip short-circuit faults in printing devices are prone to errors due to damaged chip functions, leading to incorrect short-circuit check results.
Innovation Solution
A chip design with a testing portion comprising multiple conductive terminals and a grounding terminal, where the testing portion includes line segments that electrically connect to the grounding terminal, allowing for accurate identification of short circuits and functional damage by analyzing actual output level signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the chip returns a waveform that conforms to expectation during short-circuit check, then the chip is considered not short-circuited, but when chip function is damaged, the chip cannot return the expected waveform leading to error in determining short-circuit check result
Solution Approach 1:
The chip terminal is divided into multiple independent conductive terminals (first conductive terminal, second conductive terminal, grounding terminal) with specific spatial arrangements. The testing portion includes separate testing line segments that can independently detect short circuits between different terminal pairs, allowing the system to segment the detection task and identify specific fault locations even when chip functions are damaged.
Solution Approach 2:
The testing portion acts as an intermediary component between the conductive terminals and the external testing device. It includes testing line segments that provide dedicated testing paths independent of the chip's normal communication functions, enabling short-circuit detection without relying on the chip's functional waveforms.
2Area of stationary object
If conductive terminals are arranged close together to reduce chip size, then the chip becomes more compact, but the risk of short circuit between adjacent terminals increases
Solution Approach 1:
The chip substrate is divided into first and second half regions with different functional characteristics. The first half region contains the grounding terminal with specific quality characteristics for short-circuit protection, while the second half region contains conductive terminals arranged for compact layout. This local differentiation allows compact design while maintaining safety through region-specific design rules.
Solution Approach 2:
The testing portion with testing line segments serves as an intermediary safety mechanism between closely arranged conductive terminals. These testing lines provide dedicated detection paths that can identify short circuits between adjacent terminals, enabling the system to safely pack terminals close together while maintaining detection capability through the intermediary testing structure.
3Measurement precision
If a testing portion is added to detect short circuits between conductive terminals, then short-circuit detection capability is improved, but the chip structure becomes more complex
Solution Approach 1:
The testing portion is merged with the existing chip structure by integrating testing line segments into the substrate layout. The testing lines are combined with the terminal arrangement, sharing the same physical space and manufacturing process, thereby achieving short-circuit detection functionality without adding separate discrete components or significantly increasing structural complexity.
Solution Approach 2:
The testing line segments serve multiple functions: they provide short-circuit detection paths between conductive terminals, act as part of the overall electrical connection structure, and can be integrated into the chip's testing and debugging infrastructure. This multi-functionality reduces the need for separate dedicated testing components, thereby limiting the increase in device complexity.
Data Source
AI summary
A chip short-circuit check method and apparatus, a chip testing method, and a chip and a consumable box are provided. The chip includes a substrate, a grounding terminal, at least two conductive terminals, and a testing portion. The substrate has a first half region and a second half region. The grounding terminal includes a ground wire contact portion configured to be in contact with a stylus of a printer, and located in the first half region. The at least two conductive terminals are located in the second half region and arranged spaced apart from each other. Each conductive terminal includes a contact portion configured to be in contact with the stylus of the printer. The testing portion is located on the substrate and electrically connected to the grounding terminal. The testing portion includes a first testing line segment located between a first conductive terminal and a second conductive terminal.