Alternating Printhead Bus Segmentation for Voltage Drop Compensation
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Solution Overview
Problem
Existing inkjet printheads face challenges in providing uniform voltage to drop ejectors due to parasitic voltage drops, especially when drop ejectors are widely spaced, leading to nonuniform drop ejection and potential damage to heating elements, and existing solutions either require additional components, increase size and cost, or compromise print speed.
Innovation Solution
The implementation of a configuration with alternating drop ejector arrays connected to separate power and current return bus lines, along with strategic placement of auxiliary bus lines and compensation resistors, to minimize parasitic voltage drops and ensure uniform voltage distribution across the printhead, allowing for high-speed printing with uniform drop ejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power bus line is used for all drop ejectors, then the device complexity is reduced, but parasitic voltage drop variations increase causing nonuniform drop ejection
Solution Approach 1:
The power bus system is segmented into multiple separate power bus lines, with each line serving a specific subset of drop ejectors. This segmentation reduces the current load on each individual bus line, thereby minimizing parasitic voltage drops and ensuring more uniform voltage delivery to all drop ejectors across the printhead array.
2Reliability
If drop ejectors are widely spaced to reduce fluidic interaction, then drop ejection uniformity improves, but parasitic voltage drop variations increase
Solution Approach 1:
The power bus configuration is optimized locally for different regions of the printhead. Drop ejectors in different spatial locations are assigned to different power bus lines based on their specific electrical characteristics and position-dependent parasitic resistance. This local optimization ensures that each drop ejector receives appropriate voltage compensation for its specific location, maintaining uniform drop ejection across the entire array.
3Reliability
If additional compensation components are added to reduce parasitic voltage drop, then voltage uniformity improves, but device size and complexity increase
Solution Approach 1:
The power bus system is designed to create equipotential conditions across all drop ejector locations. By strategically configuring multiple power bus lines with optimized routing and connection points, the system minimizes potential differences between different drop ejectors, effectively compensating for parasitic voltage drops without requiring additional active compensation components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic voltage drop variations, enabling reliable and uniform drop ejection across the printhead, compatible with high-speed printing and extending actuator lifetime without requiring additional input/output terminals or increasing the device's size and complexity.
Implementation Method 1
A heating element 35, which functions as the actuator, is formed on the surface of the base plate 10 within each pressure chamber 22. Heating element 35 is configured to selectively pressurize the pressure chamber 22 by rapid boiling of a portion of the ink in order to eject drops of ink through the nozzle 32
Implementation Method 2
The power bus and the current return bus are made of an electrically conductive material such as aluminum. However, they are typically on the order of one to two microns thick. As a result, their resistance can be several ohms, which is not an insignificant fraction of the resistance of the heating element 35. The resistance in the bus lines is sometimes called parasitic resistance. When one or more actuators are fired, the current through the bus lines results in parasitic voltage drops.
Data Source
AI summary
A drop ejector array device includes a first plurality and a second plurality of drop ejectors that are alternatingly disposed along an array direction on the substrate surface. A voltage input terminal and a current return terminal are disposed on the substrate surface. A first power bus line connects the first plurality to the voltage input terminal. A second power bus line connects the second plurality to the voltage input terminal. The second power bus line is electrically connected to the first power bus line by a primary power bus connector line. A first current return bus line connects the first plurality to the current return terminal. A second current return bus line connects the second plurality to the current return terminal. The second current return bus line is electrically connected to the first current return bus line by a primary current return bus connector line.