A Priori Corner and Mode Reduction for IC Timing Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity and size of integrated circuit designs lead to a rapid increase in the time required to fix design requirement violations due to the growing number of scenarios over which circuit designs need to be checked, particularly in modern circuit designs with multiple operating modes and process corners.
Innovation Solution
The approach involves creating synthetic corners and modes to reduce the number of active scenarios, allowing for optimization over a reduced set of corners and modes, thereby improving runtime performance by capturing critical timing effects without activating multiple corners or modes, and using static analysis to decompose scenario reduction into corner and mode reduction problems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of process corners and operating modes is increased to ensure comprehensive design verification, then the reliability of design compliance checking is improved, but the optimization runtime and total turn-around-time increase rapidly
Solution Approach 1:
The patent performs preliminary static analysis to identify and eliminate redundant corners and modes before the main optimization process. By analyzing the circuit design in advance to determine which corners and modes are actually necessary, the method reduces the number of scenarios that need to be checked during optimization, thereby reducing runtime while maintaining verification completeness.
Solution Approach 2:
The patent extracts and removes redundant corners and modes from the verification set by analyzing the circuit design characteristics. Through static analysis, it identifies corners and modes that do not contribute additional verification value and eliminates them from the optimization process, reducing the computational burden while preserving design compliance assurance.
2Manufacturing precision
If all corner and mode combinations are checked to ensure design robustness, then the manufacturing precision is improved, but the device complexity increases
Solution Approach 1:
The patent performs preliminary static analysis to determine the minimal necessary set of corners and modes before optimization. By analyzing the circuit design characteristics in advance, it identifies which corners and modes are actually needed for verification, reducing the apparent complexity while maintaining comprehensive coverage of critical scenarios.
Solution Approach 2:
The patent extracts redundant corners and modes from the verification set through static analysis of the circuit design. It removes scenarios that do not provide additional verification value, thereby reducing the number of scenarios from 48 to a smaller subset that maintains design robustness verification.
3Productivity
If the number of active scenarios is reduced to improve runtime performance, then the productivity is improved, but the measurement precision of timing analysis may be compromised
Solution Approach 1:
The patent performs preliminary static analysis to accurately determine which corners and modes are necessary for timing verification. This advance analysis ensures that the reduced set of active scenarios still captures all critical timing paths and constraints, maintaining measurement precision while improving productivity.
Solution Approach 2:
The patent uses static analysis as an intermediary step between full verification and reduced verification. This intermediary analysis accurately identifies the minimal necessary scenarios, serving as a bridge that preserves timing analysis precision while enabling runtime performance improvement through scenario reduction.
Data Source
AI summary
Systems and techniques are described for performing a priori corner and mode reduction. Some embodiments create a synthetic corner in which (1) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple temperature corners, and/or (2) a cell delay for each library cell in a set of library cells corresponds to a maximum delay over multiple parasitic corners. Some embodiments can identifying, for a given corner, a portion of the circuit design that is common across multiple modes, and then replace the multiple modes with a single mode for optimizing and verifying timing constraints of the portion of the circuit design that is common across the multiple modes. The circuit design can then be optimized over the reduced set of modes and/or corners.