Prioritized Soft Constraint Solving for Semiconductor Design Verification
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Solution Overview
Problem
Current design verification tools for semiconductor circuits are inefficient in detecting errors, especially in large complex systems, as they struggle to scale and often fail to properly stimulate designs due to contradictory or incompatible constraints, leading to increased costs and errors as design phases progress.
Innovation Solution
A computer-implemented method for prioritizing soft constraints in semiconductor design, which involves obtaining and recognizing constraints, prioritizing them, solving the design problem, and identifying unsatisfied soft constraints, with the ability to debug and report root causes, allowing for resource allocation and caching solutions within global resource limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If constrained random verification is used to gauge functionality of complex circuits, then verification coverage is improved, but constraint compatibility and solution satisfaction deteriorate due to contradictory constraints
Solution Approach 1:
The patent changes the parameter of constraint satisfaction from binary (satisfied/not satisfied) to prioritized levels. By assigning priorities to soft constraints, the system can satisfy higher-priority constraints while allowing lower-priority ones to be violated, thus resolving contradictions between competing constraints and improving overall verification effectiveness.
Solution Approach 2:
The patent introduces dynamic constraint satisfaction where the system adapts to constraint conflicts by selectively satisfying constraints based on their priorities. The verification process dynamically adjusts which constraints must be met versus which can be relaxed, enabling the system to handle complex, contradictory constraints in large-scale circuit verification.
2Reliability
If extensive analysis and verification are performed to ensure circuit compliance, then design correctness is improved, but verification time and computational resources increase
Solution Approach 1:
The patent applies partial action by selectively verifying against the most critical constraints rather than attempting to satisfy all constraints equally. By focusing verification efforts on high-priority soft constraints and essential hard constraints, the system achieves adequate verification coverage without the prohibitive time cost of exhaustive verification of all constraints.
Solution Approach 2:
The patent segments the verification process by dividing constraints into hard constraints (must be satisfied) and soft constraints (prioritized for satisfaction). This segmentation allows the verification system to efficiently handle different constraint types with appropriate strategies, reducing overall verification time while maintaining design correctness.
3Ease of operation
If test benches apply fixed sequences of test vectors to verify circuit outputs, then verification simplicity is maintained, but error detection capability deteriorates for complex modern circuits
Solution Approach 1:
The patent transitions from static fixed test vector sequences to dynamic constrained random test vector generation. The system dynamically generates test vectors that adapt to the circuit under verification and the active constraints, improving error detection capability while maintaining ease of operation through automated constraint-based generation.
Solution Approach 2:
The patent introduces feedback mechanisms where constraint satisfaction results and verification outcomes feed back into the test vector generation process. This feedback enables the system to learn from previous verification attempts and generate more effective test vectors, improving error detection while keeping the verification process manageable through automated adjustment.
Data Source
AI summary
A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored.