Priority Arbitration Binary Trees for Scalable Request Selection
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Solution Overview
Problem
Existing arbiters face inefficiencies and increased delays as the number of requestors increases, leading to reduced throughput and hardware size expansion, particularly in round robin arbitration schemes where not all requestors submit requests in every cycle.
Innovation Solution
A binary decision tree-based arbiter generates select signals using valid and priority bits, combined through AND logic elements, followed by pair-wise OR-reduction to efficiently select requestors, reducing hardware size and compile/synthesis time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a round robin arbitration scheme is used to ensure fair access for all requestors, then all requestors are granted access over time, but the arbitration delay increases and throughput decreases as the number of requestors increases
Solution Approach 1:
The patent segments the arbitration process into multiple levels: a first arbiter handles a subset of requestors, while a second arbiter handles another subset. This hierarchical segmentation allows each arbiter to make decisions more quickly on smaller groups, reducing overall arbitration delay while maintaining fairness through the structured multi-level approach
Solution Approach 2:
The patent introduces a hierarchical dimension to the arbitration structure by organizing requestors into groups with different arbitration levels. Requestors are arbitrated through multiple stages (first arbiter, second arbiter, and potential third arbiter), adding a temporal and structural dimension that reduces the complexity of single-cycle arbitration for large numbers of requestors
2Productivity
If the number of requestors increases to handle more traffic, then system capacity increases, but arbitration delay and hardware complexity increase
Solution Approach 1:
The patent divides the arbitration hardware into multiple separate arbiters (first arbiter, second arbiter, third arbiter) that each handle specific subsets of requestors. This segmentation allows the system to scale to more requestors without requiring a single complex arbiter, as each individual arbiter remains relatively simple while collectively handling a large number of requestors
Solution Approach 2:
The patent implements dynamic arbitration where the selection process adapts based on which requestors are currently active and their priority levels. The multi-level arbitration structure dynamically routes requests through different arbitration paths, allowing the system to efficiently handle varying numbers of active requestors without fixed hardware complexity
3Speed
If priority-based arbitration is implemented to improve response time for high-priority requestors, then critical requests are handled faster, but the complexity of the arbitration logic increases
Solution Approach 1:
The patent segments the priority arbitration logic across multiple arbiters, where each arbiter handles priority decisions for its subset of requestors. This distributes the complex priority logic across several simpler components rather than requiring one highly complex arbiter, maintaining fast priority response while managing complexity through modular design
Solution Approach 2:
The patent adds a hierarchical dimension to priority arbitration by implementing multiple levels of arbiters (first, second, and third arbiters) that process priority requests at different stages. This multi-dimensional approach allows priority handling to be distributed across temporal and structural dimensions, reducing the complexity burden on any single arbitration logic unit
Data Source
AI summary
Methods of arbitrating between requestors and a shared resource wherein for each processing cycle a plurality of select signals are generated and then used by decision nodes in a binary decision tree to select a requestor. The select signals are generated using valid bits and priority bits. Each valid bit corresponds to one of the requestors and indicates whether, in the processing cycle, the requestor is requesting access to the shared resource. Each priority bit corresponds one of the requestors and indicates whether, in the processing cycle, the requestor has priority. Corresponding valid bit and priority bits are combined in an AND logic element to generate a valid_and_priority bit for each requestor. Pair-wise OR-reduction is then performed on both the valid bits and the valid_and_priority bits to generate additional valid bits and valid_and_priority bits for sets of requestors and these are then used to generate the select signal.