Hierarchical Priority Buffer for Memory Fabric Packet Transfer

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Solution Overview

Problem

Traffic bottlenecks occur in memory fabrics due to the disparity in data rates and link widths between the physical layer interfaces of memory fabrics and other devices, such as those using PCIe interfaces, leading to inefficiencies in packet traffic management.

Innovation Solution

An apparatus and method that prioritize packet traffic on cross-physical layer interfaces by using a hierarchical ordered priority buffer structure, where atomic requests are queued in a high-priority buffer and other packets in a lower-priority buffer, with configuration registers defining priority memory regions and maintaining access counts to optimize memory fabric physical layer interface usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If packet traffic is managed using a standard FIFO buffer structure, then the device complexity is low, but the latency for atomic requests increases due to traffic bottlenecks

Engineering Contradiction:
Improvelatency for atomic requestsVSAvoidbuffer structure complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The buffer structure is segmented into multiple priority buffers (first priority buffer for atomic requests, second priority buffer for other packets) instead of using a single FIFO buffer. This segmentation allows atomic requests to be handled separately and prioritized, reducing their latency while maintaining manageable complexity through modular buffer design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality of service is provided to different types of packets based on their priority. Atomic requests receive high-priority handling with dedicated buffer space and processing precedence, while other packets use lower-priority buffers. This local quality differentiation resolves the latency issue for critical atomic operations without unnecessarily complicating the handling of all packet types.

Inventive Principle:
Principle #3Local quality

2Productivity

If high-data-rate memory fabric interfaces are used, then the productivity increases, but energy efficiency deteriorates due to unnecessary processing of all packet types at high speed

Engineering Contradiction:
Improvepacket transfer rateVSAvoidenergy efficiency
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system applies high-data-rate processing selectively to only those packets that require it (atomic requests in the first priority buffer), rather than processing all packets at maximum speed. This partial action approach maintains high productivity for critical operations while reducing energy consumption by not over-processing lower-priority packets.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The processing parameters (data rate, priority level) are changed based on packet type. Atomic requests are processed with high data rate and high priority parameters, while other packets use lower parameters. This dynamic parameter adjustment optimizes both productivity and energy efficiency by matching processing intensity to actual requirements.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If atomic requests are prioritized over other packets, then the reliability of atomic operations improves, but the device complexity increases due to priority management mechanisms

Engineering Contradiction:
Improveatomic operation reliabilityVSAvoidpriority management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The priority management mechanism is simplified through segmentation into distinct priority buffers with clear separation of functions. The first priority buffer is dedicated exclusively to atomic requests, while the second buffer handles other packets. This segmentation provides reliable atomic operation handling without requiring complex priority arbitration logic, as the buffer separation inherently enforces priority.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4070203B1Apparatus and methods for managing packet transfer across a memory fabric physical layer interface
Publication Date: 2024.07.10 ADVANCED MICRO DEVICES INC
  • EP4070203B1 patent drawingFigure 1
  • EP4070203B1 patent drawingFigure 2~6
  • EP4070203B1 patent drawingFigure 3

AI summary

An apparatus and method for managing packet transfer between a memory fabric having a physical layer interface higher data rate than a data rate of a physical layer interface of another device, receives incoming packets from the memory fabric physical layer interface wherein at least some of the packets include different instruction types. The apparatus and method determine a packet type of the incoming packet received from the memory fabric physical layer interface and when the determined incoming packet type is of a type containing an atomic request, the method and apparatus prioritizes transfer of the incoming packet with the atomic request over other packet types of incoming packets, to memory access logic that accesses local memory within an apparatus.