Multi-processor Message Transfer via Priority Buffer Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing multi-processor systems face challenges in efficiently transferring messages between processors, including prioritization of messages and delays in releasing message storage regions, which affect communication throughput.

Innovation Solution

A multi-processor system with priority buffer regions that classify messages based on priority levels, allowing processors to manage and access messages efficiently by checking and writing messages to free regions in shared memory, and enabling simultaneous management by different processors to reduce access conflicts and delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a single message buffer is used with FIFO method, then message sequence is maintained, but message priority cannot be reflected

Engineering Contradiction:
Improvemessage sequenceVSAvoidmessage priority reflection
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The single message buffer is segmented into multiple priority buffer regions (first priority buffer region, second priority buffer region, etc.), each handling messages of different priority levels. This segmentation allows the system to maintain FIFO ordering within each priority level while enabling priority-based message handling across regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different buffer regions are assigned different qualities based on priority levels. The first priority buffer region handles high-priority messages while the second priority buffer region handles lower-priority messages, allowing each region to have optimized characteristics for its specific priority level while working together as a unified buffer system.

Inventive Principle:
Principle #3Local quality

2Device complexity

If the releasing process is performed by the transmission processor only, then management simplicity is maintained, but time difference and delay occur

Engineering Contradiction:
Improvemanagement processVSAvoidtime difference
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The releasing process is merged with the reception processor's operations. When the reception processor reads a message from the buffer, it simultaneously performs the releasing process for the corresponding buffer region. This combining of operations eliminates the time difference between transmission-side release and reception-side acknowledgment.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The reception processor performs the releasing process as part of its own message reading operation, making the system self-synchronizing. The reception processor automatically manages the release state based on its own operations, eliminating the need for separate release notifications and reducing time differences.

Inventive Principle:
Principle #25Self-service

3Productivity

If multiple processors independently manage buffer regions, then throughput is improved, but access conflicts occur

Engineering Contradiction:
ImprovethroughputVSAvoidaccess conflict
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The buffer management is segmented by assigning specific buffer regions to specific processors. Each processor manages only the buffer regions assigned to it, eliminating conflicts between processors while maintaining independent management capabilities. This segmentation allows multiple processors to operate simultaneously without interfering with each other's buffer access.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different buffer regions have different management characteristics assigned based on their assigned processor. Each buffer region is optimized for the specific processor that manages it, allowing independent management with guaranteed non-conflicting access patterns while maintaining overall system throughput.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7613197B2Multi-processor system and message transferring method in the same
Publication Date: 2009.11.03 RENESAS ELECTRONICS CORP
  • US7613197B2 patent drawing
  • US7613197B2 patent drawing
  • US7613197B2 patent drawing

AI summary

A multi-processor system includes a plurality of processors; and a memory section connected with the plurality of processors and configured to store a message transmitted from each of the plurality of processor to another. The memory section has a plurality of priority buffer regions corresponding to a plurality of priority levels, and the message is classified based on a priority level allocated to the message. Each of the plurality of priority buffer regions stores the message having the priority level corresponding to the buffer region.