Priority-Based Cache Line Fitting in Compressed Memory
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Solution Overview
Problem
Conventional data compression systems in processor-based systems incur performance overhead due to the need for metadata access and additional address computation, which increases complexity, cost, and latency when accessing cache lines in memory.
Innovation Solution
The method involves partitioning memory regions into priority-based data regions, compressing cache lines, and using overflow pointers to manage data that exceeds predetermined sizes, reducing the need for metadata and optimizing cache line access by utilizing overflow blocks of varying sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data compression is used to increase memory bandwidth, then effective memory capacity increases, but memory access latency and system complexity increase due to metadata access and address computation
Solution Approach 1:
The patent extracts and eliminates the metadata component from the compression system. By using priority-based cache line fitting where compressed cache lines are directly placed in predetermined portions of candidate compressed cache lines, the system removes the need for separate metadata structures that map virtual addresses to physical addresses, thereby eliminating metadata access overhead and reducing memory access latency
Solution Approach 2:
The patent segments the memory region into multiple data regions with different priority levels. High priority cache lines are allocated to first predetermined portions while low priority cache lines are allocated to second predetermined portions. This segmentation enables direct address calculation without metadata lookup, reducing access latency while maintaining compression benefits
2Quantity of substance
If metadata is used for address mapping in compression systems, then data can be stored in compressed format, but device complexity and cost increase
Solution Approach 1:
The patent removes the metadata component entirely from the compression architecture. Instead of using metadata to map virtual addresses to physical addresses of compressed data, the system uses direct priority-based allocation where the address calculation is simplified to only require the base address of the data region and the priority level, significantly reducing system complexity
Solution Approach 2:
The priority field that would traditionally be used only for QoS purposes is given multiple functions: it serves both as a quality of service indicator and as an address calculation parameter. This multi-functionality eliminates the need for separate metadata structures, reducing both complexity and cost while maintaining compression capabilities
3Adaptability or versatility
If metadata access is required for compressed data, then address mapping can be performed, but productivity decreases due to additional reads and writes
Solution Approach 1:
The patent extracts and eliminates the metadata access step from the memory access path. By using priority-based cache line fitting with predetermined portions for different priority levels, the system calculates physical addresses directly from virtual addresses using only the priority field and base address, removing the need for metadata reads and writes and thereby improving memory access throughput
Solution Approach 2:
The system performs preliminary organization of cache lines into priority-based data regions during the compression process. Candidate compressed cache lines are pre-divided into first predetermined portions for high priority lines and second predetermined portions for low priority lines. This preliminary organization enables direct address calculation during read/write operations without requiring subsequent metadata access, improving productivity
Data Source
AI summary
A compressed memory system of a processor-based system includes a memory partitioning circuit for partitioning a memory region into data regions with different priority levels. The system also includes a cache line selection circuit for selecting a first cache line from a high priority data region and a second cache line from a low priority data region. The system also includes a compression circuit for compressing the cache lines to obtain a first and a second compressed cache line. The system also includes a cache line packing circuit for packing the compressed cache lines such that the first compressed cache line is written to a first predetermined portion and the second cache line or a portion of the second compressed cache line is written to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.