Priority Fault Replacement in Memory Arrays for Low-Voltage CNNs

Solution Overview

Problem

Low-power convolutional neural networks (CNN) accelerators face accuracy issues due to stuck-at faults in SRAM cells when supply voltage is low, particularly affecting low-bitwidth floating-point CNNs accessing data from SRAM devices.

Innovation Solution

Implementing a value-aware error-detecting boundary and error-correcting pointer system to verify and selectively replace faulty SRAM cells based on priority, using a neural network processor, test circuit, redundancy analyzer, and storage circuit to ensure accurate data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If dynamic voltage scaling is applied to reduce power consumption, then power consumption is reduced, but stuck-at faults occur in SRAM cells when supply voltage is low

Engineering Contradiction:

Improvepower consumptionVSAvoidSRAM cell reliability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by performing built-in self-test (BIST) operations before the neural network processor executes its workload. The BIST circuit identifies and replaces faulty SRAM cells in advance, creating a reliable subset of memory cells that can be safely used during low-voltage operation. This preliminary identification and replacement of faulty cells ensures that subsequent computing operations at reduced voltage levels will not encounter stuck-at faults.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service through the built-in self-test (BIST) functionality that is integrated within the memory device itself. The BIST circuit autonomously tests SRAM cells, identifies stuck-at faults, and triggers replacement operations without requiring external testing equipment or intervention. This self-diagnostic and self-repair capability enables the memory device to maintain reliability during dynamic voltage scaling operations.

Inventive Principle:

Principle #25Self-service

2Device complexity

If low-bitwidth floating-point CNNs are used to reduce computational complexity, then device complexity is reduced, but accuracy deteriorates due to stuck-at faults

Engineering Contradiction:

Improvecomputational complexityVSAvoidCNN output accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by performing built-in self-test (BIST) operations before the neural network processor executes its workload. The BIST circuit identifies and replaces faulty SRAM cells in advance, creating a reliable subset of memory cells that can be safely used during low-voltage operation. This preliminary identification and replacement of faulty cells ensures that subsequent computing operations at reduced voltage levels will not encounter stuck-at faults.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service through the built-in self-test (BIST) functionality that is integrated within the memory device itself. The BIST circuit autonomously tests SRAM cells, identifies stuck-at faults, and triggers replacement operations without requiring external testing equipment or intervention. This self-diagnostic and self-repair capability enables the memory device to maintain reliability during dynamic voltage scaling operations.

Inventive Principle:

Principle #25Self-service

3Speed

If SRAM cells are used for high-speed data access, then speed is improved, but stuck-at faults occur at low supply voltage

Engineering Contradiction:

Improvedata access speedVSAvoidSRAM cell reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by performing built-in self-test (BIST) operations before the neural network processor executes its workload. The BIST circuit identifies and replaces faulty SRAM cells in advance, creating a reliable subset of memory cells that can be safely used during low-voltage operation. This preliminary identification and replacement of faulty cells ensures that subsequent computing operations at reduced voltage levels will not encounter stuck-at faults.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service through the built-in self-test (BIST) functionality that is integrated within the memory device itself. The BIST circuit autonomously tests SRAM cells, identifies stuck-at faults, and triggers replacement operations without requiring external testing equipment or intervention. This self-diagnostic and self-repair capability enables the memory device to maintain reliability during dynamic voltage scaling operations.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS12399644B2Memory device

Publication Date: 2025.08.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory device is provided, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.