Priority Interrupt Controller Emulating Non-Maskable Interrupts
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Solution Overview
Problem
The transition from x86 to ARM64 processors poses difficulties for operating systems due to the lack of non-maskable interrupts (NMIs) in the ARM64 core ISA and Generic Interrupt Controller (GIC), which are essential for maintaining system functions like TLB maintenance and performance monitoring.
Innovation Solution
Implementing a pseudo non-maskable interrupt (PNMI) mechanism that distinguishes between regular and PNMI interrupts, allowing PNMI handling even when regular interrupts are disabled, and enabling PNMI delivery as an inter-processor interrupt, thereby emulating NMI behavior without altering existing operating system functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ARM64 processor with GIC is used instead of x86 processor, then device compatibility and mobile platform support are improved, but the ability to handle non-maskable interrupts is lost
Solution Approach 1:
The patent introduces a priority interrupt controller as an intermediary layer between the GIC and the processor cores. This controller intercepts interrupt requests from the GIC and selectively routes them to processor cores based on priority levels. By assigning the highest priority level to specific interrupt requests, the system emulates NMI behavior where high-priority interrupts can be delivered even when lower-priority interrupts are masked, thus resolving the contradiction between using ARM64 architecture and maintaining NMI functionality.
2Stability of the object's composition
If regular interrupt masking is implemented, then interrupt prioritization and system stability are improved, but the delivery of critical non-maskable interrupts is prevented
Solution Approach 1:
The patent segments the interrupt handling system into multiple priority levels. The priority interrupt controller divides interrupt requests into different priority categories, with regular interrupts at lower priorities and critical interrupts (emulating NMIs) at the highest priority. This segmentation allows the system to mask lower-priority interrupts during critical sections while ensuring that highest-priority interrupts can still be delivered, thus maintaining both system stability and critical interrupt delivery.
3Adaptability or versatility
If NMI functionality is emulated using priority interrupts, then operating system compatibility is maintained, but the processor architecture remains unchanged
Solution Approach 1:
The priority interrupt controller is designed to work with the existing GIC architecture while adding NMI emulation capabilities. The same interrupt controller hardware handles both regular interrupts and emulated NMIs, making the system universal. The controller interprets certain interrupt requests as highest-priority NMIs based on interrupt vector identification, allowing a single device to serve multiple functions and reducing overall system complexity despite the added functionality.
Data Source
AI summary
A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.