Priority Selection Circuit Concurrent Validation

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Solution Overview

Problem

Existing digital communication systems face longer propagation delays due to the serial process of obtaining a priority signal and then selecting the data input with the highest priority from multiple valid data inputs.

Innovation Solution

A novel data selection circuit that simultaneously prioritizes and selects the data input with the highest priority by using a switch control module, detection module, and selection multiplexer to validate and route data signals based on preselected priorities, allowing for concurrent validation and selection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a two-stage serial process is used to first encode priority signals and then select data inputs, then the selection can be performed systematically, but the propagation delay increases

Engineering Contradiction:
Improvepropagation delayVSAvoidselection process complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent combines the priority encoding function and data selection function into a single integrated circuit block. The switch control module performs both priority determination and selection routing simultaneously, eliminating the need for separate encoding and selection stages, thus reducing propagation delay while maintaining systematic selection capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The circuit pre-establishes priority relationships among multiple data inputs through the switch control module's internal logic structure. By having the control module ready with priority information and validation rules before data arrival, the system can perform simultaneous validation and selection in one pass, avoiding sequential processing delays

Inventive Principle:
Principle #10Preliminary action

2Speed

If simultaneous prioritization and selection is implemented, then operational speed improves, but the device complexity increases

Engineering Contradiction:
Improveoperational speedVSAvoidcircuit structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The switch control module is designed as a multi-functional unit that simultaneously performs data validation, priority determination, and selection routing. This universal module handles multiple tasks in parallel without requiring separate dedicated circuits for each function, achieving high operational speed while controlling complexity through functional integration

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent divides the selection circuit into modular components: validation inputs, switch control module, and multiplexer. Each module has a specific function but works in tight integration, allowing the system to achieve complex simultaneous prioritization and selection through coordinated simple modules rather than a monolithic complex structure

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7817653B2Priority selection circuit
Publication Date: 2010.10.19 MEIZU TECH CO LTD
  • US7817653B2 patent drawing
  • US7817653B2 patent drawing
  • US7817653B2 patent drawing

AI summary

A circuit includes a first selection module having first data input, second data input, first validation input, second validation input, selected data output, marker output, and presence output. A first validation signal received at the first validation input identifies whether or not a first data signal received at the first data input is valid; a second validation signal received at the second validation input identifies whether or not a second data signal received at the second data input is valid; a presence signal outputted at the presence output identifies whether or not at least one data signal is valid; and the first data input has an assigned selection priority higher than that assigned to the second data input. If at least one data signal is identified as valid, the valid data signal having the higher assigned priority is transferred to the selected data output.