Private Cache Allocation for Power-Collapsed Processor Cores
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Solution Overview
Problem
In multicore processor-based systems, the unavailability of private caches during power-collapsed states leads to decreased processor performance and inaccurate benchmark results due to increased cache access latency and reduced cache utilization.
Innovation Solution
Implementing a snoop controller that maintains power to the private cache and enables allocation and snooping by other processor cores when a core enters a power-collapsed state, allowing the private cache to remain online and accessible for data-caching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a processor core is placed in a power-collapsed state to reduce power consumption, then power efficiency is improved, but the corresponding private cache becomes unavailable resulting in decreased processor performance
Solution Approach 1:
The patent separates the power control of the processor core from the power control of its private cache by creating independent power domains. The core power domain can be collapsed to save power while the cache power domain remains active, allowing the cache to continue serving other cores. This segmentation resolves the contradiction by enabling independent power management of core and cache resources.
Solution Approach 2:
The private cache is designed to serve multiple functions: it acts as a private cache for its associated core when active, but can simultaneously serve as a shared cache resource for other active cores when the associated core is power-collapsed. The snoop controller enables this multi-functionality by allowing other cores to allocate and snoop the cache lines of power-collapsed cores' caches, thus maintaining processor performance while enabling power savings.
2Loss of time
If private caches are allocated exclusively to individual processor cores to reduce arbitration latency, then cache access latency is improved, but cache utilization decreases when cores are power-collapsed
Solution Approach 1:
The patent introduces dynamic cache allocation where cache accessibility is not fixed but changes based on the power state of associated cores. When a core is active, its cache is privately allocated; when a core is power-collapsed, its cache dynamically becomes accessible to other cores. The snoop controller manages this dynamic allocation, allowing the system to optimize between exclusive access (low latency) and shared access (high utilization) based on real-time power states.
3Productivity
If private caches remain powered on during core power-collapsed states to maintain cache availability, then processor performance is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by maintaining power to specific cache resources that are still useful (those needed by other active cores) while allowing power collapse for resources that are not needed (caches of idle cores). The snoop controller enables fine-grained control, allowing individual cache lines or sets to remain accessible based on their utilization by other cores, thus optimizing the local power-performance tradeoff for each cache resource independently.
Data Source
AI summary
Providing private cache allocation for power-collapsed processor cores in processor-based systems is provided. In one aspect, a processor-based system provides multiple processor cores, each residing within its own processor core power domain. Each processor core is provided with a private cache residing within its own private cache power domain, configured to be power-controlled independently of the corresponding processor core power domain. When a first processor core is placed in a power-collapsed state, a snoop controller corresponding to the private cache of the first processor core maintains power to the private cache power domain of the private cache, allowing the private cache to remain online. The snoop controller also enables allocation and snooping of the private cache by a second processor core while the first processor core remains in the power-collapsed state. In this manner, each private cache may be used for data-caching operations while its corresponding processor core is power-collapsed.