Private Memory Table for Reduced Coherence Traffic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current multiple processor data processing systems face scalability issues with snoopy-based cache coherence protocols, leading to increased memory coherence traffic and bandwidth demands, while directory-based protocols are expensive to implement and result in large memory coherence directories as systems grow.
Innovation Solution
Implementing a private region table (PRT) mechanism that allows processors to identify and manage private memory regions, reducing the need for snooping and coherence overhead by using a node walk instead of a system pump for memory access, and maintaining memory coherence through directed remote memory access and virtualization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If snoopy-based cache coherence protocols are used, then cache coherence is maintained, but memory coherence traffic and bandwidth demands increase
Solution Approach 1:
The patent segments the memory address space into private regions and shared regions. The private region table (PRT) tracks which memory regions are private to each processor, allowing the system to bypass snooping for private accesses while maintaining coherence for shared regions. This segmentation reduces unnecessary snooping traffic while preserving cache coherence where needed.
Solution Approach 2:
The patent applies different coherence protocols to different memory regions. For private memory regions, no snooping is performed, reducing traffic. For shared memory regions, full snooping coherence is maintained. This local differentiation optimizes the balance between coherence requirements and traffic reduction.
2Productivity
If directory-based coherence protocols are used, then scalability is improved, but implementation cost and directory size increase
Solution Approach 1:
The patent extracts the directory functionality and replaces it with a private region table (PRT) that is much smaller and simpler. Instead of maintaining a comprehensive directory of all memory regions and their cache states across the system, each processor maintains a compact PRT that only tracks private regions, significantly reducing complexity while improving scalability.
3Reliability
If snooping is performed for all memory accesses, then cache coherence is ensured, but bandwidth consumption increases
Solution Approach 1:
The patent dynamically adjusts the coherence protocol based on the memory region being accessed. The private region table allows the system to dynamically switch between snooping and non-snooping modes depending on whether the accessed memory is private or shared, optimizing bandwidth usage while maintaining coherence when necessary.
Data Source
AI summary
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.