Private Page Tracking in Multiprocessor Cache Coherency

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Solution Overview

Problem

In multiprocessing computer systems, broadcast cache coherency protocols face performance bottlenecks due to high network bandwidth usage, especially with large numbers of processors or frequent probes, as they require broadcasting messages to all processors, whereas directory-based protocols reduce traffic but can still benefit from enhanced probe filtering.

Innovation Solution

A system and method that include a processor with interface logic and a memory controller, which uses an address translation storage structure to track private pages, inhibiting probe messages for write requests to pages not mapped by other processors and issuing specific probes only when necessary, reducing unnecessary network traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If broadcast cache coherency protocol is used, then coherency maintenance is simplified, but network bandwidth consumption increases significantly

Engineering Contradiction:

Improvecoherency maintenance simplicityVSAvoidnetwork bandwidth consumption

Core Design Contradiction:

Ease of operationVSLoss of energy

Solution Approach 1:

The patent applies local quality by differentiating the treatment of different memory pages based on their access patterns. Pages are classified as private or shared based on whether multiple processors access them, and different probe strategies are applied to each class. This localized differentiation reduces unnecessary probes to processors that do not access particular pages, thereby reducing overall network bandwidth consumption while maintaining coherency where needed.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements preliminary action by maintaining private page indications in address translation storage structures before coherence conflicts occur. These indications are updated in advance during memory access operations, allowing the memory controller to pre-determine which processors need to receive probes. This advance preparation eliminates the need for broadcasting probes to all processors, reducing network traffic while ensuring coherency is maintained when required.

Inventive Principle:

Principle #10Preliminary action

2Loss of energy

If directory-based protocol is used, then network traffic is reduced, but probe filtering efficiency can be improved

Engineering Contradiction:

Improvenetwork traffic reductionVSAvoidprobe filtering efficiency

Core Design Contradiction:

Loss of energyVSProductivity

Solution Approach 1:

The patent applies feedback by using private page indications stored in address translation storage structures to guide future probe decisions. The memory controller receives feedback about which pages are privately accessed by which processors and uses this information to optimize probe routing. This feedback mechanism allows the system to learn from past access patterns and make more efficient probe filtering decisions, improving productivity while maintaining reduced network traffic.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent implements preliminary action by pre-storing private page indications in address translation storage structures before coherence operations are needed. These indications are maintained and updated in advance, allowing the memory controller to quickly determine which processors should receive probes without needing to perform extensive real-time analysis. This advance preparation improves probe filtering efficiency while maintaining the network traffic reduction benefits of directory-based protocols.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If probes are broadcast to all processors, then coherency is ensured, but bandwidth bottleneck occurs

Engineering Contradiction:

Improvecoherency assuranceVSAvoidbandwidth consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent extracts the essential coherency information needed to ensure reliability by using private page indications stored in address translation storage structures. These indications contain the critical information about which processors access which pages, allowing the system to extract and transmit only this necessary information through targeted probes rather than broadcasting to all processors. This extraction approach maintains coherency assurance while significantly reducing bandwidth consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS7669011B2Method and apparatus for detecting and tracking private pages in a shared memory multiprocessor

Publication Date: 2010.02.23 ADVANCED MICRO DEVICES INC

AI summary

A processor includes a processor core coupled to an address translation storage structure. The address translation storage structure includes a plurality of entries, each corresponding to a memory page. Each entry also includes a physical address of a memory page, and a private page indication that indicates whether any other processors have an entry, in either a respective address translation storage structure or a respective cache memory, that maps to the memory page. The processor also includes a memory controller that may inhibit issuance of a probe message to other processors in response to receiving a write memory request to a given memory page. The write request includes a private page attribute that is associated with the private page indication, and indicates that no other processor has an entry, in either the respective address translation storage structure or the respective cache memory, that maps to the memory page.