Privilege-Based Access Control for Shared Bus Peripherals
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Solution Overview
Problem
In multicore processing systems, existing shared bus architectures face challenges in managing access to system peripherals, leading to potential resource conflicts and inefficiencies, particularly in ensuring secure access and optimal resource utilization.
Innovation Solution
Implementing access control logic based on privilege levels to dynamically allocate and re-allocate shared peripherals among processing cores, using a global system configuration register and controller identifiers to manage access and prevent unauthorized modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a shared bus architecture is used to connect multiple processing cores to system peripherals, then resource utilization and system efficiency are improved, but access conflicts and security risks arise when multiple cores attempt to modify critical peripherals simultaneously
Solution Approach 1:
The patent implements dynamic access control where the shared bus controller can change the operational state of peripherals in real-time based on core privilege levels and current system conditions. The controller dynamically switches between shared access mode and exclusive access mode, allowing flexible resource allocation while maintaining security. This dynamic approach enables the system to adapt access permissions on-the-fly without requiring static configuration or physical isolation of peripherals.
2Reliability
If private buses are used for system peripherals to avoid resource conflicts, then access security and reliability are improved, but device complexity and die area increase due to duplication of peripheral modules
Solution Approach 1:
The patent introduces a shared bus controller as an intermediary between processing cores and system peripherals. This controller acts as a smart mediator that manages all access requests, enforces security policies, and coordinates simultaneous access needs. By placing this intelligent intermediary in the data path, the system maintains a shared bus architecture while achieving security levels previously only possible with private buses. The controller mediates conflicts by granting exclusive access to authorized cores while blocking unauthorized access attempts.
3Ease of operation
If any processing core can access shared peripherals without restriction, then ease of operation and flexibility are improved, but unauthorized modifications and system instability occur
Solution Approach 1:
The patent applies different access control policies to different peripherals based on their criticality and security requirements. The shared bus controller evaluates each access request individually, considering the target peripheral's security attributes and the requesting core's privilege level. This local quality approach means that critical peripherals receive strict access control while less sensitive peripherals maintain broader accessibility. The system thus provides tailored access control rather than a one-size-fits-all approach, optimizing both security and operational flexibility for each specific peripheral.
Data Source
AI summary
A system may include a plurality of processing cores, a target shared among the plurality of processing cores and coupled to the plurality of processing cores via a shared bus, and access control logic configured to, based on access configuration settings associated with the target, control access of requests from each of the plurality of processing cores based on a privilege level of each of the plurality of processing cores, in order to dynamically allocate and re-allocate the target among the plurality of processing cores in accordance with the privilege levels and to dynamically utilize the target in accordance with the privilege levels.