Privilege Mapping for Scalable Memory Access Protection
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Solution Overview
Problem
Current memory management units in computing systems face challenges such as complexity in design and verification, variable performance, inflexibility in scaling, and a large memory footprint due to small page sizes, especially in large multiprocessor systems where physical addresses exceed the 32-bit range.
Innovation Solution
A distributed memory management and protection system that uses a 'Privilege Identifier' (PRVID) to select memory segments and allows flexible mapping, enabling CPUs to manage their own memory segments and DMA requests, thereby reducing bottlenecks and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory management units with page-oriented architecture are used, then memory protection and address translation functions are provided, but the system becomes complicated to design and verify
Solution Approach 1:
The patent divides the memory management function into separate components: privilege checking is performed by dedicated privilege indicators associated with memory segments, while address translation is handled separately. This segmentation allows each component to be verified independently, reducing overall system verification complexity while maintaining memory protection reliability.
Solution Approach 2:
The patent introduces privilege indicators as intermediary elements that mediate between memory requestors and the memory management unit. These indicators carry privilege information through the memory hierarchy, allowing protection decisions to be made at multiple levels without requiring a single complex verification mechanism.
2Productivity
If memory management unit is tightly integrated at CPU/L1 cache boundary for best performance, then memory system performance is optimized, but flexibility to scale is reduced
Solution Approach 1:
The patent implements local privilege checking at each memory segment level using locally associated privilege indicators, rather than requiring centralized control. This allows performance optimization at local boundaries while maintaining the flexibility to scale the system architecture, as each segment can operate semi-independently with its own protection mechanisms.
3Manufacturing precision
If small page sizes (4 KB) are used in memory management, then fine-grained memory control is achieved, but large memory footprint is required for page table entries
Solution Approach 1:
The patent implements partial privilege checking where not all memory segments require full privilege verification. By using privilege indicators that can be selectively applied based on segment characteristics, the system achieves fine-grained control where needed while reducing the overhead of privilege table entries for segments that don't require strict protection, thereby reducing overall memory footprint.
4Quantity of substance
If conventional memory management units are used in large multiprocessor systems with 32 bit processors, then address translation is provided, but physical address space is limited to 32 bit range
Solution Approach 1:
The patent extends the address space by adding a new dimension to the address translation mechanism. Privilege indicators are incorporated into the address translation process, allowing the system to translate 32-bit logical addresses to larger physical address spaces while maintaining security. This adds a dimensional layer to traditional address translation, enabling beyond-32-bit addressing without fundamentally redesigning the translation unit.
Data Source
AI summary
A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission.