Privileged VM Functions for Inter-Processor Interrupt Routing
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Solution Overview
Problem
In virtualized computer systems, transmitting inter-processor interrupt messages typically requires a VM exit, which incurs significant overhead and affects system efficiency.
Innovation Solution
The implementation of privileged virtual machine functions that allow inter-processor interrupt messages to be transmitted without performing a VM exit, using a notification code module and task mapping data structure to identify and write IPI messages into APIC registers, with validation to ensure correctness and avoid unnecessary VM exits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional VM exit method is used to transmit inter-processor interrupt messages, then system control and security are maintained, but processing latency increases and system efficiency decreases
Solution Approach 1:
The hypervisor pre-configures privileged VM function entries in the VMCS before VM execution. When an IPI message needs to be transmitted, the guest VM can directly invoke the pre-configured VM function to write to APIC registers without requiring VM exit, thus eliminating the time loss while maintaining controlled access through hypervisor configuration.
Solution Approach 2:
The patent introduces privileged VM functions as an intermediary mechanism between the guest VM and the hardware APIC registers. These VM functions act as mediators that allow controlled access to privileged hardware without requiring full VM exit, thus reducing latency while maintaining system security through hypervisor-defined access rights.
2Reliability
If VM exit is performed for interrupt message transmission, then privileged access is obtained, but processing overhead increases
Solution Approach 1:
The hypervisor pre-configures the VMCS with entries for privileged VM functions that map to safe hardware access paths. This preliminary configuration allows the guest VM to invoke these functions directly without VM exit, obtaining privileged access efficiency while avoiding the overhead of repeated VM exit/entry cycles.
Solution Approach 2:
The patent changes the execution mode parameter from full VM exit to privileged VM function invocation. By modifying how privileged access is obtained (from context switch to direct function call), the system maintains security through hypervisor-configured access while significantly reducing processing overhead and improving productivity.
3Productivity
If privileged VM functions are used without validation, then processing speed improves, but system security and correctness may be compromised
Solution Approach 1:
The hypervisor performs preliminary validation by pre-configuring which VM functions are allowed to access privileged hardware. This advance authorization mechanism enables fast direct invocation of validated functions while maintaining security, as the validation is performed once during configuration rather than on each access.
Solution Approach 2:
The system implements feedback through hypervisor monitoring of VM function invocations. The hypervisor tracks which VM functions are called and ensures they correspond to pre-approved entries in the VMCS, providing continuous feedback that maintains security while allowing high-speed operation through validated paths.
Data Source
AI summary
Systems and methods for transmitting inter-processor interrupt messages by privileged virtual machine functions. An example method may comprise: mapping, by a hypervisor being executed by a processing device of a host computer system, a plurality of interrupt controller registers of the host computer system into a memory address space of a virtual machine being executed by the host computer system; mapping, into the memory address space of the virtual machine, a task mapping data structure comprising a plurality of records, each record associating a task with a processor of the host computer system; and mapping, into the memory address space of the virtual machine, a notification code module to be invoked by the virtual machine for writing a notification message into an interrupt controller register associated with a processor identified using the task mapping data structure.