Pseudo-random Number Generator Combinatorial Logic Circuit
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Solution Overview
Problem
Existing pseudo-random number generators (PRNGs) face challenges in achieving uniform probability distribution and efficiency, particularly in hardware implementation, due to the need for complex logic operations and potential systematic failures in bit reversal tests.
Innovation Solution
A pseudo-random number generator design utilizing combinatorial logic circuits, including XOR and XNOR gates, AND, and OR gates, to generate random numbers by combining bits from two registers in a way that eliminates the need for addition operations, ensuring non-linear output and efficient hardware implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PRNG methods are used, then random number generation is achieved, but uniform probability distribution and efficiency are compromised due to complex logic operations and systematic failures in bit reversal tests
Solution Approach 1:
The patent divides the random number generation process into separate functional stages: a linear feedback shift register (LFSR) component for generating bit sequences, and a non-linear combination component for producing final random numbers. This segmentation allows each component to be optimized independently, with the LFSR providing efficient bit generation and the combination logic ensuring uniform distribution without complex operations.
Solution Approach 2:
The patent introduces an intermediary combination logic layer between the LFSR output and the final random number output. This intermediary component processes the bit sequences from the LFSR through simple combinatorial logic (AND, OR, NOT gates) to produce uniformly distributed random numbers, avoiding the need for complex arithmetic operations while maintaining reliability.
2Productivity
If complex logic operations are used in PRNG, then random number generation capability is improved, but hardware resource requirements and implementation efficiency deteriorate
Solution Approach 1:
The patent replaces complex arithmetic operations (addition, multiplication) with simpler combinatorial logic operations (AND, OR, NOT gates). This substitution is achieved by implementing the random number generation function through a LFSR-based system that uses bitwise operations and simple logic gates, significantly reducing hardware resource requirements while maintaining generation efficiency.
Solution Approach 2:
The patent changes the operational parameters from arithmetic operations to logical operations. Instead of using addition and multiplication to combine bits, the system uses XOR, AND, OR, and NOT operations. This parameter change enables efficient hardware implementation with fewer logic gates and lower resource consumption, while still achieving uniform probability distribution.
3Reliability
If conventional PRNG approaches are used, then random number generation is achieved, but systematic failures occur in bit reversal tests
Solution Approach 1:
The patent addresses bit reversal test failures by inverting the approach: instead of trying to make the output resistant to bit reversal through complex operations, the system uses a LFSR-based approach where the bit reversal property is inherently managed by the shift register structure. The combination logic is designed to work correctly regardless of bit order, ensuring pass in bit reversal tests without complicating the implementation.
Data Source
AI summary
A pseudo random number generator implemented in hardware. The pseudo random number generator comprises a state post processing circuit for processing two state values to produce a random number. The circuit having a first combinatorial logic comprising a XOR or XNOR gate configured to process a first pair of bits from the state values, a second combinatorial logic comprising an OR or AND gate configured to process a second pair of bits from the state value, and third combinatorial logic comprising an OR or AND gate configured or process a third pair of bits from the state value. The circuit has fourth combinatorial logic configured to process the outputs of the first three set of combinatorial logic so as to provide a result bit of the random number. The fourth combinatorial logic comprises an AND or OR gate and a XOR or XNOR gate.