Pseudo-Random Number Generator Using Multiple Shift Registers

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Solution Overview

Problem

Existing random number generators require a large chip area and significant hardware resources to produce a predefined number of random bits per clock cycle, making them costly and inefficient for applications like smartcards that need multiple random bytes per cycle.

Innovation Solution

A pseudo-random number generator using multiple non-linear feedback shift registers (NLFSRs) with transformation functions that compress and combine output vectors to generate statistically independent random bits efficiently, reducing hardware requirements and chip area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional random number generators are used to produce a predefined number of random bits per clock cycle, then the required randomness output is achieved, but the chip area and hardware resources become excessively large

Engineering Contradiction:

Improverandom bits per clock cycleVSAvoidchip area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The random number generator is divided into multiple independent Linear Feedback Shift Registers (LFSRs), each generating a portion of the random bits. This segmentation allows the system to achieve high throughput by operating multiple registers in parallel while keeping each individual register compact, thus resolving the contradiction between productivity and chip area.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple LFSRs are combined through a merging function that collects output bits from all registers and assembles them into the final random number output. This merging approach enables the system to produce more random bits per clock cycle than a single register could generate, while the total area remains manageable because each component register is smaller than a single large register would be.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If more shift registers are used to increase random bits output, then productivity improves, but device complexity increases

Engineering Contradiction:

Improverandom bytes per clock cycleVSAvoidnumber of shift registers

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Each LFSR is designed to be a universal, identical module that can be replicated multiple times. The same structure and feedback polynomial are used for all registers, making them interchangeable and simplifying the overall design. This universality allows the system to scale productivity by simply adding more identical modules rather than designing increasingly complex single-register structures.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

A merging function acts as an intermediary between the multiple LFSRs and the final output. This mediator collects bits from all registers, applies any necessary transformations, and produces the final random number. The intermediary simplifies the complexity management by providing a standardized interface that abstracts the underlying multiple-register complexity from the output requirement.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10754617B2Generating of random numbers

Publication Date: 2020.08.25 INFINEON TECHNOLOGIES AG

AI summary

A device for generating a random number is suggested, the device comprising at least two shift registers, a transformation function that generates the random number based on at least one cell of each of the at least two shift registers.