PRNGCMP Instruction Vector Histogram Generation
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Solution Overview
Problem
Current vector instructions, such as PCMPxESTy, are limited in generating histograms as they produce mask vectors rather than count vectors, requiring multiple instructions to scale bin sizes and population sizes, which is inefficient and resource-intensive.
Innovation Solution
The PRNGCMP instruction generates a vector resultant corresponding to counts within bins by comparing population units against bin ranges, using masking logic to identify applicable elements and accumulate counts, allowing for efficient histogram creation with fewer instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current vector instructions (PCMPxESTy) are used to generate histograms, then mask vectors are produced, but multiple instructions are required to scale bin sizes and population sizes
Solution Approach 1:
The patent combines multiple separate operations (comparison, masking, scaling, and counting) into a single vector instruction PRNGCMP. This merging eliminates the need for multiple sequential instructions to generate histograms, directly producing count vectors that represent histogram bins while incorporating scaling factors and population size adjustments within the same instruction execution.
Solution Approach 2:
The PRNGCMP instruction is designed to perform multiple functions simultaneously: it compares population units against bin ranges, applies scaling factors to bin sizes, accounts for population size, and generates count vectors all in one operation. This multi-functionality replaces what previously required several separate instructions, reducing computational complexity while maintaining histogram generation accuracy.
2Measurement precision
If multiple instructions are used to scale bin sizes and population sizes, then histogram generation is possible, but processing efficiency decreases
Solution Approach 1:
The patent merges scaling operations for both bin sizes and population sizes into the single PRNGCMP instruction. The instruction accepts scaling factors as inputs and incorporates them during the comparison and counting process, eliminating the need for separate scaling instructions and thereby improving processing efficiency while maintaining accurate histogram bin scaling.
Solution Approach 2:
The PRNGCMP instruction performs scaling preparations internally before generating the final count vectors. By pre-computing scaled bin ranges and incorporating population size adjustments within the instruction execution flow, the patent eliminates the need for preliminary separate scaling operations, thus improving productivity without sacrificing measurement precision.
3Reliability
If mask vectors are produced instead of count vectors, then comparison results are obtained, but additional processing is required to generate histograms
Solution Approach 1:
Instead of producing mask vectors and then converting them to count vectors through additional processing, the patent inverts the approach by directly producing count vectors as the output of the PRNGCMP instruction. This inversion eliminates the intermediate mask vector step while maintaining the reliability of comparison results, as the instruction internally performs the comparison logic and directly accumulates counts based on comparison outcomes.
Solution Approach 2:
The patent combines the comparison operation with the count generation operation in the single PRNGCMP instruction. Rather than separating these into distinct steps (comparison producing masks, then masks converted to counts), the merging allows the instruction to perform comparisons and directly generate count vectors in one unified operation, improving histogram generation speed while preserving comparison accuracy.
Data Source
AI summary
A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.