Proactive Cache Coherence via Speculative Permission Prediction

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Solution Overview

Problem

In distributed shared-memory computing systems, cache coherence operations introduce performance overhead due to the need for processors to obtain coherence permissions before accessing memory, leading to delayed memory access times as they wait for coherence communications to complete.

Innovation Solution

Implementing predictors at processor cores and directories to proactively predict future memory access patterns and speculatively initiate coherence operations, such as predicting addresses of future accesses and requesting coherence permissions before actual memory access requests, thereby reducing the need for coherence-related stalls.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If processors wait for coherence permissions before memory access, then cache coherence is maintained, but memory access time increases

Engineering Contradiction:
Improvecache coherenceVSAvoidmemory access time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary coherence operations by having directory predictors proactively request coherence permissions for predicted future memory accesses before the actual memory access occurs. This preliminary action allows coherence permissions to be obtained in advance, eliminating the need for processors to wait during actual memory access operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The coherence protocol operations are segmented into two distinct phases: speculative coherence operations initiated by directory predictors for predicted accesses, and actual memory access operations. This segmentation allows coherence management to occur independently in advance, decoupling it from the critical memory access path and reducing waiting time.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If coherence operations are performed on demand, then system complexity is reduced, but performance overhead increases

Engineering Contradiction:
Improvecoherence protocol complexityVSAvoidmemory access performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

Directory predictors perform preliminary analysis of memory access patterns and proactively initiate coherence operations for predicted future accesses. This preliminary action transforms the traditional on-demand coherence model into a predictive model, reducing performance overhead by preparing coherence permissions in advance based on observed access patterns.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where directory predictors monitor actual memory access patterns and use this feedback to refine future predictions. This feedback loop allows the system to adapt to changing access patterns while maintaining reduced coherence latency through continued proactive coherence operations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10162757B2Proactive cache coherence
Publication Date: 2018.12.25 ADVANCED MICRO DEVICES INC
  • US10162757B2 patent drawing
  • US10162757B2 patent drawing
  • US10162757B2 patent drawing

AI summary

A distributed shared-memory system includes several nodes that each have one or more processor cores, caches, local main memory, and a directory. Each node further includes predictors that use historical memory access information to predict future coherence permission requirements and speculatively initiate coherence operations. In one embodiment, predictors are included at processor cores for monitoring a memory access stream (e.g., historical sequence of memory addresses referenced by a processor core) and predicting addresses of future accesses. In another embodiment, predictors are included at the directory of each node for monitoring memory access traffic and coherence-related activities for individual cache lines to predict future demands for particular cache lines. In other embodiments, predictors are included at both the processor cores and directory of each node. Predictions from the predictors are used to initiate coherence operations to speculatively request promotion or demotion of coherence permissions.