Proactive Memory Probing for Network Traffic Error Recovery
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Solution Overview
Problem
Network devices experience memory errors, such as soft errors caused by single-event upsets, which disrupt network traffic processing when the affected memory is accessed by the packet processor, leading to undesired traffic drops due to the non-trivial time required for error correction.
Innovation Solution
Implement proactive memory error detection and correction mechanisms by using error detection circuitry to proactively probe memory circuitry, detecting errors before they are accessed for network traffic processing, and correcting them independently of the packet processor's access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory errors are detected only when accessed by the packet processor, then error detection is simple, but network traffic processing is disrupted due to the non-trivial time required for error correction
Solution Approach 1:
The patent implements preliminary action by having a dedicated error detection mechanism probe memory circuitry before the packet processor accesses it. This proactive detection identifies memory errors in advance, allowing the system to handle errors before they disrupt network traffic processing, thus resolving the contradiction between maintaining processing continuity and accounting for error correction time.
2Reliability
If proactive memory probing is implemented, then error detection occurs before traffic processing, but additional complexity is introduced to the memory access mechanism
Solution Approach 1:
The patent applies segmentation by separating the error detection function from the packet processing function. A dedicated error detection mechanism is implemented independently, allowing it to probe memory circuitry without interfering with the packet processor's operations. This segmentation resolves the contradiction by enabling reliable error detection while maintaining relatively simple and independent access paths.
Solution Approach 2:
The patent introduces an intermediary error detection mechanism that acts as a mediator between the memory circuitry and the packet processor. This intermediary probes memory for errors independently, providing error information to the packet processor without being part of the main data path. This resolves the contradiction by adding detection capability while keeping the intermediary's complexity isolated from the core processing path.
3Productivity
If memory errors are not proactively detected, then the system operates simpler, but traffic drops occur when corrupted memory is accessed during packet processing
Solution Approach 1:
The patent implements preliminary action by probing memory circuitry before the packet processor accesses it during normal operation. This proactive detection identifies memory errors in advance, allowing the system to handle errors before they cause traffic drops, thus maintaining both high throughput and data integrity without requiring complex error handling during active processing.
Data Source
AI summary
A network device may include data plane processing circuitry and memory circuitry accessible by the data plane processing circuitry to perform traffic processing operations. The memory circuitry may sometimes experience memory errors such as bit flips. One or more processors on the network device may access the memory circuitry, in parallel with the data plane processing circuitry accessing the memory circuitry, to detect and correct these memory errors more quickly, thereby reducing disruptions to traffic processing operations caused by memory errors.