Proactive Read Voltage Adjustment for SSD Error Recovery
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Solution Overview
Problem
Existing storage systems, particularly SSDs, face inefficiencies in error recovery due to re-read triggering, which increases latency and reduces quality of service due to Moving Read Reference (MRR) mechanisms, as they often require re-reading the same page with different read voltages, leading to prolonged error recovery times.
Innovation Solution
The implementation of proactive MRR reduction techniques, where the system adjusts read voltage shift directions and values based on error rates, using automatic read calibration and hard bit reads with level indicators to prevent MRR triggering, thereby reducing re-reads and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Moving Read Reference (MRR) mechanism is used to recover read errors, then read error correction capability is improved, but latency increases and quality of service deteriorates due to re-reading the same page with different read voltages
Solution Approach 1:
The system performs preliminary actions by proactively adjusting read reference voltages before actual read errors occur. The controller monitors error rates and voltage distributions, anticipating potential read failures and pre-adjusting voltages to prevent MRR triggering, thereby reducing error recovery time while maintaining correction capability
Solution Approach 2:
The system implements feedback mechanisms where the controller continuously monitors error rates and voltage distribution characteristics. Based on this feedback, the controller dynamically adjusts read reference voltages to optimize read operations, preventing unnecessary re-reads and reducing latency while maintaining reliable error correction
2Reliability
If re-read operations are performed with different read voltages to correct errors, then data accuracy is improved, but system latency increases
Solution Approach 1:
The system performs preliminary voltage adjustments based on monitored error patterns and voltage distributions. By proactively optimizing read voltages before errors occur, the system avoids the latency penalty of re-reading pages with different voltages, thereby reducing system latency while maintaining data accuracy
Solution Approach 2:
The system dynamically adjusts read reference voltages in real-time based on monitored error rates and voltage distributions. This dynamic optimization allows the system to adapt to changing memory conditions, preventing unnecessary re-reads and reducing latency while ensuring accurate data retrieval
Data Source
AI summary
An embodiment of a semiconductor apparatus may include technology to determine an error rate associated with a read request for a persistent storage media, compare the determined error rate against a pre-fail threshold, and adjust a read voltage shift direction for the persistent storage media if the determined error rate exceeds the pre-fail threshold. Other embodiments are disclosed and claimed.