Probabilistic Delay Clock Generation for Low-Jitter Fractional Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional clock generation circuits face challenges in achieving precise timing control with low jitter performance, particularly in fractional clock dividers, due to process variations, temperature fluctuations, and supply voltage changes, which introduce timing errors and spurious frequency components.
Innovation Solution
A clock generation circuit utilizing a numerically controlled oscillator, variable delay circuit with probabilistic delay assignment, and ratio estimation circuit to minimize jitter and spurious signals, incorporating a zero-DNL DAC configuration for linear skew control and stochastic signal processing to convert delay errors into zero-mean additive white noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional delay adjustment techniques are used in clock generation circuits, then timing control is achieved, but spurious frequency components and jitter are introduced due to non-linearities and process variations
Solution Approach 1:
The patent implements dynamic delay adjustment by making the delay element controllable through a control signal that adjusts the delay amount. This dynamic control allows the delay to be precisely tuned while maintaining linearity, thereby achieving accurate timing control without introducing spurious frequency components that would result from static or non-linear delay mechanisms
Solution Approach 2:
The patent changes the delay parameter in a linear manner with respect to the control signal. By ensuring that the delay element's delay amount varies linearly with the control signal, the system achieves precise timing control while avoiding the non-linearities that cause spurious frequency components and jitter in traditional approaches
2Measurement precision
If delay adjustment is implemented to achieve precise timing control, then timing accuracy improves, but circuit complexity increases
Solution Approach 1:
The patent introduces a delay element as an intermediary component that is controlled by a control signal. This intermediary structure allows precise timing control to be achieved through simple linear adjustment mechanisms rather than complex timing circuits, thereby improving timing precision without proportionally increasing circuit complexity
Solution Approach 2:
The dynamic nature of the delay element allows it to be controlled by a simple control signal rather than requiring complex combinatorial logic or multiple fixed delay stages. This dynamic control approach achieves precise timing adjustment with minimal additional circuit complexity
3Ease of manufacture
If conventional delay adjustment techniques are used, then implementation is simple, but timing errors occur due to process variations and temperature fluctuations
Solution Approach 1:
The patent employs a phase detector that compares the phase of the output clock signal with a reference signal and generates a control signal based on the phase difference. This feedback mechanism automatically compensates for timing errors caused by process variations and temperature fluctuations, maintaining timing stability without complicating the implementation
Solution Approach 2:
The dynamic delay adjustment mechanism allows the delay to be continuously tuned in response to environmental variations. This dynamic adaptation maintains timing stability under varying conditions while keeping the implementation relatively simple through the use of a controllable delay element rather than complex compensation circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves high spectral purity and timing accuracy with integrated jitter specifications of −61 dBc/Hz and 71 fs, ensuring precise frequency control and minimizing unwanted timing variations.
Implementation Method 1
a variable delay circuit comprising a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load
Implementation Method 2
the probabilistic delay assignment circuit converts delay errors to zero-mean additive white noise using stochastic signal processing to eliminate periodic spurious signals
Data Source
AI summary
In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities p1=m1/L and p2=(L−m1)/L for selecting the first and second delay settings, where m1 represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.