Probabilistic Error Tracking Using Hash Circuits
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Solution Overview
Problem
Semiconductor memory devices face challenges in accurately tracking and correcting errors, particularly in identifying frequent error-prone addresses, due to the impracticality of storing count values for each row address and the need for sophisticated analysis of error patterns.
Innovation Solution
The implementation of a probabilistic error tracking system using multiple hash circuits to compress row addresses into hash values, which are then used to determine problem addresses by updating count values and comparing them to thresholds, reducing the number of count values required while maintaining statistical meaningfulness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If count values are stored for each row address to accurately track errors, then error tracking precision is improved, but storage requirements and device complexity increase significantly
Solution Approach 1:
The patent introduces hash circuits as intermediary components that transform row addresses into compressed hash values. These hash values serve as mediators between the original row addresses and the count values, allowing error tracking with significantly reduced storage requirements while maintaining statistical accuracy through the hash function's properties.
Solution Approach 2:
The patent creates a compressed representation (copy) of the error tracking data structure by mapping multiple row addresses to fewer hash values. This copy maintains the essential error pattern information needed for identifying problem addresses while occupying much less storage space than the full row address count table.
2Measurement precision
If multiple hash circuits with different hash lengths are used, then collision rates are balanced and identification accuracy is improved, but device complexity increases
Solution Approach 1:
The patent divides the error tracking function into multiple parallel hash circuits, each processing row addresses through different hash functions with varying lengths. This segmentation allows the system to balance collision rates across different hash value ranges, improving overall identification accuracy while keeping individual hash circuits relatively simple.
Solution Approach 2:
The patent varies the hash length parameter across different hash circuits to optimize performance. By using hash circuits with different hash lengths (e.g., shorter and longer hashes), the system balances collision rates and improves problem address identification accuracy without requiring any single hash circuit to be overly complex.
3Reliability
If all count values are updated for every error, then error tracking completeness is improved, but processing time and energy consumption increase
Solution Approach 1:
The patent extracts only the essential error information by updating count values associated with hash values rather than maintaining complete information for every row address. This extraction approach maintains error tracking completeness for identifying problem addresses while significantly reducing the processing overhead and energy consumption associated with updating and managing count values.
Data Source
AI summary
Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes.