Probabilistic Set Associative Cache Hit Rate Optimization

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Solution Overview

Problem

Direct-mapped caches exhibit lower hit rates compared to set-associative caches, leading to performance issues in very large DRAM-based cache memories, which are also complex and power-hungry.

Innovation Solution

The Probabilistic Set Associative Cache (PAC) operates as a direct-mapped cache most of the time but temporarily converts to a 2-way cache for sets with frequent misses, using a novel cache replacement algorithm and additional tag bit to achieve (1+P)-way set associativity, reducing miss rates and maintaining direct-mapped cache complexity and power requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If set-associative cache organization is used to improve hit rate, then cache performance is improved, but hardware complexity and power consumption increase

Engineering Contradiction:
Improvehit rateVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cache dynamically switches between direct-mapped and set-associative modes based on the override probability parameter P. Each cache set can function as either a direct-mapped set or a 2-way set-associative set with probability P, allowing the system to adapt between simplicity and performance without requiring full set-associative hardware

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention introduces a probability parameter P (override probability) that controls the behavior of cache sets. By adjusting this parameter, the cache can tune its associativity level, transitioning from deterministic direct-mapped behavior to probabilistic set-associative behavior, thereby optimizing the trade-off between complexity and hit rate

Inventive Principle:
Principle #35Parameter changes

2Reliability

If set-associative cache organization is used to improve hit rate, then cache performance is improved, but power consumption increases

Engineering Contradiction:
Improvehit rateVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The cache dynamically activates set-associative behavior only with probability P, rather than maintaining full set-associative hardware continuously. This probabilistic activation reduces average power consumption while still achieving improved hit rates when the associative mode is activated

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Instead of implementing full set-associative caching, the invention applies set-associative behavior partially with probability P. This partial application of set-associative logic provides enough performance improvement while keeping power consumption and hardware complexity close to direct-mapped caches

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If direct-mapped cache organization is used to reduce complexity, then hardware complexity is reduced, but hit rate decreases

Engineering Contradiction:
Improvehardware complexityVSAvoidhit rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The invention modifies the deterministic direct-mapped behavior by introducing a probability parameter P. With probability P, cache sets behave as 2-way set-associative sets instead of strict direct-mapped sets, thereby improving hit rate while maintaining overall simplicity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention creates a logical copy of the direct-mapped cache structure but modifies its replacement policy to include probabilistic set-associative behavior. This allows the cache to maintain the simple physical structure of direct-mapped caches while emulating set-associative performance characteristics through software-controlled replacement algorithms

Inventive Principle:
Principle #26Copying

4Device complexity

If direct-mapped cache organization is used to maintain simplicity, then device complexity is reduced, but cache performance decreases

Engineering Contradiction:
ImprovesimplicityVSAvoidcache performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The cache dynamically adjusts its operation mode based on the override probability P, switching between simple direct-mapped operation and more sophisticated set-associative operation. This dynamic behavior allows the cache to maintain simplicity when possible while achieving better performance when needed

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

By introducing the probability parameter P, the invention transforms the static direct-mapped cache into a probabilistic system that can adapt its behavior. This parameter change enables the cache to achieve set-associative performance characteristics while maintaining the structural simplicity of direct-mapped caches

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10019370B2Probabilistic associative cache
Publication Date: 2018.07.10 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10019370B2 patent drawing
  • US10019370B2 patent drawing
  • US10019370B2 patent drawing

AI summary

A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.