Probe Board Tilt Alignment for Accurate Wafer Testing

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Solution Overview

Problem

Existing wafer testing apparatuses struggle to accurately align probe boards with wafers, leading to inadequate contact and inaccurate testing of semiconductor devices.

Innovation Solution

A wafer testing apparatus equipped with a camera to capture images of probe and wafer imaging points, allowing for precise measurement and adjustment of the probe board tilt, and a controller to align the probe board with the wafer based on image information, thereby improving contact and accuracy in testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional alignment methods are used without image capture, then the device complexity is reduced, but the manufacturing precision of probe board alignment deteriorates

Engineering Contradiction:
Improveprobe board alignment precisionVSAvoidalignment system complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent uses a camera to capture images of imaging points on the probe board and wafer, creating visual copies of their positions. These image copies are then processed to calculate tilt angles and alignment deviations, enabling precise alignment measurement without direct physical measurement tools.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent replaces traditional mechanical alignment measurement methods with an optical imaging system. Instead of using mechanical gauges or physical contact measurement, the system uses camera imaging to detect positions of imaging points, thereby substituting mechanical measurement with optical detection for non-contact, high-precision alignment.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If tilt measurement and adjustment are not performed, then the operation process is simplified, but the testing accuracy of semiconductor devices deteriorates

Engineering Contradiction:
Improvetesting accuracyVSAvoidalignment operation complexity
Core Design Contradiction:
Manufacturing precisionVSEase of operation

Solution Approach 1:

The patent implements a feedback mechanism where the camera captures images of imaging points, the controller calculates tilt angles based on these images, and then adjusts the probe board tilt accordingly. This closed-loop feedback system automatically corrects alignment deviations, improving testing accuracy while managing operational complexity through automation.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs tilt measurement and adjustment before the actual semiconductor device testing begins. By pre-aligning the probe board to match the wafer tilt using imaging points captured before testing, the system ensures optimal alignment is established in advance, thereby improving testing accuracy without adding complexity during the testing operation itself.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12566193B2Wafer testing apparatus and control method thereof
Publication Date: 2026.03.03 SAMSUNG ELECTRONICS CO LTD
  • US12566193B2 patent drawing
  • US12566193B2 patent drawing
  • US12566193B2 patent drawing

AI summary

A wafer testing apparatus includes a probe board disposed above a chamber, a wafer chuck disposed below the probe board and configured to support the wafer, a camera located between the probe board and the wafer chuck and configured to capture images of probe imaging points arranged on a lower surface of the probe board and wafer imaging points arranged on an upper surface of the wafer, and a controller electrically connected to the camera and configured to adjust a tilt of the probe board on the basis of image information acquired by the camera. The probe imaging points include a plurality of probe outer imaging points arranged in a rhombic pattern on the lower surface of the probe board, and the wafer imaging points include a plurality of wafer outer imaging points arranged in a rhombic pattern on the upper surface of the wafer.